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Temperature-aware microarchitecture
- In Proceedings of the 30th Annual International Symposium on Computer Architecture
, 2003
"... With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processor-level techniques that can regulate operating temperature when the package’s capacity is exceeded. Evaluating such techn ..."
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Cited by 469 (51 self)
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With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processor-level techniques that can regulate operating temperature when the package’s capacity is exceeded. Evaluating such techniques, however, requires a thermal model that is practical for architectural studies. This paper describes HotSpot, an accurate yet fast model based on an equivalent circuit of thermal resistances and capacitances that correspond to microarchitecture blocks and essential aspects of the thermal package. Validation was performed using finiteelement simulation. The paper also introduces several effective methods for dynamic thermal management (DTM): “temperaturetracking” frequency scaling, localized toggling, and migrating computation to spare hardware units. Modeling temperature at the microarchitecture level also shows that power metrics are poor predictors of temperature, and that sensor imprecision has a substantial impact on the performance of DTM. 1.
Hotspot: a dynamic compact thermal model at the processor architecture level. Microelectronics Journal: Circuit and Systems
, 2003
"... This paper describes a thermal-modeling approach that is easy to use and computationally efficient for modeling thermal effects and thermal-management techniques at the processor architecture level. Our approach is based on modeling thermal behavior of the micropro-cessor die and its package as a ci ..."
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Cited by 21 (6 self)
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This paper describes a thermal-modeling approach that is easy to use and computationally efficient for modeling thermal effects and thermal-management techniques at the processor architecture level. Our approach is based on modeling thermal behavior of the micropro-cessor die and its package as a circuit of thermal resistances and capacitances that corre-spond to functional blocks at the architecture level. This yields a simple compact model, yet heat dissipation within all major functional blocks and the heat flow among blocks and through the package are accounted for. The model is parameterized, boundary- and initial-conditions independent, and is derived by a structure assembly approach. The architecture community has demonstrated growing interest in thermal management, but currently lacks a way to model on-chip temperatures in a tractable way. Our model can be used for initial exploration of the design space at the architecture level. The model can easily be integrated into popular power/performance simulators, can be used to determine how thermal stress is correlated to the architecture, and how architecture-level design decisions influence thermal behavior and related effects.
Temperature-aware resource allocation and binding in high-level synthesis
- in Proc. Design Automation Conf
, 2005
"... Physical phenomena such as temperature have an increasingly important role in performance and reliability of modern process technologies. This trend will only strengthen with future generations. Attempts to minimize the design effort required for reaching closure in reliability and performance const ..."
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Cited by 19 (2 self)
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Physical phenomena such as temperature have an increasingly important role in performance and reliability of modern process technologies. This trend will only strengthen with future generations. Attempts to minimize the design effort required for reaching closure in reliability and performance constraints are agreeing on the fact that higher levels of design abstractions need to be made aware of lower level physical phenomena. In this paper, we investigated techniques to incorporate temperature-awareness into high-level synthesis. Specifically, we developed two temperature-aware resource allocation and binding algorithms that aim to minimize the maximum temperature that can be reached by a resource in a design. Such a control scheme will have an impact on the prevention of hot spots, which in turn is one of the major hurdles in front of reliability for future integrated circuits. Our algorithms are able to reduce the maximum attained temperature by any module in a design by up to 19.6oC compared to a binding that optimizes switching power.
Peak Temperature Control and Leakage Reduction During Binding
- in High Level Synthesis”. In Procs of ISLPED
, 2005
"... Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness of such lower level physical phenomenon in high level synthesis algorithms will help to achieve better designs. In this wo ..."
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Cited by 5 (1 self)
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Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness of such lower level physical phenomenon in high level synthesis algorithms will help to achieve better designs. In this work, we developed a temperature aware binding algorithm. Switching power of a module correlates with its operating temperature. The goal of our binding algorithm is to distribute the activity evenly across functional units. This approach avoids steep temperature differences between modules on a chip, hence, the occurrence of hot spots. Starting with a switching optimal binding solution, our algorithm iteratively minimizes the maximum temperature reached by the hottest functional unit. Our algorithm does not change the number of resources used in the original binding. We have used HotSpot, a temperature modeling tool, to simulate temperature of a number ASIC designs. Our binding algorithm reduces temperature reached by the hottest resource by 12.21°C on average. Reducing the peak temperature has a positive impact on leakage as well. Our binding technique improves leakage power by 11.89%, and overall power by 3.32% on average at 130nm technology node compared to a switching optimal binding.
Thermal Modeling and Management of Microprocessors
, 2009
"... The most recent, and arguably one of the most difficult obstacles to the exponential growth in transistor density predicted by Moore’s Law is that of removing the large amount of heat generated within the tiny area of a microprocessor. The exponential increase in power density and its direct relatio ..."
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Cited by 2 (0 self)
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The most recent, and arguably one of the most difficult obstacles to the exponential growth in transistor density predicted by Moore’s Law is that of removing the large amount of heat generated within the tiny area of a microprocessor. The exponential increase in power density and its direct relation to on-chip temperature have, in recent processors, led to very high cooling costs. Since temperature also has an exponential effect on lifetime reliability and leakage power, it has become a first-class design constraint in microprocessor development akin to performance. This dissertation describes work to address the temperature challenge from the perspective of the architecture of the microprocessor. It proposes both the infrastructure to model the problem and several mechanisms that form part of the solution. This research describes HotSpot, an efficient and extensible microarchitectural thermal modeling tool that is used to guide the design and evaluation of various thermal management techniques. It presents several Dynamic Thermal Management (DTM) schemes that distribute heat both over time and space by controlling the level of computational activity. Processor temperature is not only a function of the power density but also the placement and adjacency of hot and cold functional blocks, determined by the floorplan of the microprocessor. Hence, this dissertation also explores various thermally mitigating placement choices
TEMPERATURE AWARE TECHNIQUES FOR DESIGN, SIMULATION AND MEASUREMENT IN MICROPROCESSORS Approved as to style and content by:
, 2007
"... I am deeply indebted to my advisor, Israel Koren, for his research guidance as well as moral support. He has been an outstanding advisor. I thank Israel Koren for his careful reading of every detail of my dissertation. I would like to thank Professors Israel Koren, C. Mani Krishna, Csaba Andras Mori ..."
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I am deeply indebted to my advisor, Israel Koren, for his research guidance as well as moral support. He has been an outstanding advisor. I thank Israel Koren for his careful reading of every detail of my dissertation. I would like to thank Professors Israel Koren, C. Mani Krishna, Csaba Andras Moritz and Charles C. Weems for serving in my committee. I thank them for their thoughtful suggestions and comments. Special thanks to Dr. Z. Koren for her helpful suggestions. I must thank Israel Koren and C. Mani Krishna for their leadership in ARTS group. They have been providing us an enjoyable research environment. I enjoyed doing research with Israel Koren, C. Mani Krishna, and Csaba Andras Moritz. Their insights in system research inspired me and will benefit my career in the long run. I am also grateful to Xing Li who was my master thesis advisor in China. I built a solid background in electronic engineering during my work with him in Tsinghua University. Finally, I thank my parents, and my wife Linna, for their love, patience and support during my graduate life. iv
An integrated approach to thermal management in high-level synthesis
- IEEE Trans. on VLSI
"... Abstract—Thermal effects are becoming an important factor in the design of integrated circuits due to the adverse impact of temperature on performance, reliability, leakage, and chip packaging costs. Making all phases of the design flow aware of this physical phenomenon helps in reaching faster desi ..."
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Abstract—Thermal effects are becoming an important factor in the design of integrated circuits due to the adverse impact of temperature on performance, reliability, leakage, and chip packaging costs. Making all phases of the design flow aware of this physical phenomenon helps in reaching faster design closure. In this paper, we present an integrated approach to thermal management in architectural synthesis. Our synthesis flow combines temperatureaware scheduling and binding based on feedback from thermal simulation. We show that our flow is effective in preventing hotspot formation and creating an even thermal profile of the resources. Our integrated thermal management technique on average reduces the peak temperature of the resources by 7.34 C when compared to a thermal unaware flow without increasing the number of resources across our set of benchmarks. Index Terms—Architectural synthesis, resource allocation, resource assignment, scheduling, temperature. I.
A Computer-Architecture Approach to Thermal Management in Computer Systems: Opportunities and Challenges
"... Cooling costs for notebook, desktop, and server com-puter systems are rising exponentially as power densities for high-pegormanee chips continue to double every three years. Research has led to a range of advances in model-ing and design of thermal packaging and circuit boards. Yet a major front tha ..."
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Cooling costs for notebook, desktop, and server com-puter systems are rising exponentially as power densities for high-pegormanee chips continue to double every three years. Research has led to a range of advances in model-ing and design of thermal packaging and circuit boards. Yet a major front that has been absent is thermal de-sign in the computer architecture domain, where proces-sor utilization, the interleaving of different computation processes, and the $ow of instructions through the CPU are controlled. The architecture domain presents a rich opportunity for thermal management that complements other advances by controlling temperature at runtime in response to the dynamic behavior of the computer’s cur-rent workload. This paper describes a compact modeling algorithm that is appropriate for this domain, presents some architecture techniques for runtime thermal man-agement, and describes some interesting problems that remain to be solved. 1.
Early Quality Assessment for Low Power Behavioral Synthesis
, 2005
"... Fast and effective exploration at the early stages of the design flow can yield significant improve-ment in the quality of the design and substantial reduction in design time. In this paper, we present an efficient technique to evaluate the power dissipation of scheduled Data Flow Graphs (DFGs). Sch ..."
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Fast and effective exploration at the early stages of the design flow can yield significant improve-ment in the quality of the design and substantial reduction in design time. In this paper, we present an efficient technique to evaluate the power dissipation of scheduled Data Flow Graphs (DFGs). Scheduling dictates the compatibility of operations with respect to their assignments to functional units. Generally for scheduled DFGs, this relation is captured in the form of a comparability graph. As a consequence, the topology of the comparability graph determines the solution space available to the subsequent binding stage. In this work, our main contribution is a technique to assess the inherent flexibility of the schedules we start with. We developed early evaluation metrics in order to assess the degree of flexibility inherent in an initial schedule that will eventually affect the qual-ity of the binding solution. Every schedule is associated with a compatibility graph that represents the conflicts and compatibilities among operations with respect to possible binding decisions. Our metric based evaluation technique is based on several properties (such as edge connectivity, edge weight distribution, etc.) of these compatibility graphs. These metrics essentially reflect the amount of freedom that is provided to the binding stage, which enables early assessment and relative comparison of different possible schedules without actually performing the resource-binding step.
Contents lists available at ScienceDirect Sustainable Computing: Informatics and Systems
"... journal homepage: www.elsevier.com/locate/suscom ..."
