Results 1 - 10 of 12

FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs

by Jason Cong, Yuzheng Ding - IEEE TRANS. CAD , 1994
"... The field programmable gate-array (FPGA) has become an important technology in VLSI ASIC designs. In the past a few years, a number of heuristic algorithms have been proposed for technology mapping in lookup-table (LUT) based FPGA designs, but none of them guarantees optimal solutions for general Bo ..."
Abstract - Cited by 321 (41 self) - Add to MetaCart
The field programmable gate-array (FPGA) has become an important technology in VLSI ASIC designs. In the past a few years, a number of heuristic algorithms have been proposed for technology mapping in lookup-table (LUT) based FPGA designs, but none of them guarantees optimal solutions for general Boolean networks and little is known about how far their solutions are away from the optimal ones. This paper presents a theoretical breakthrough which shows that the LUT-based FPGA technology mapping problem for depth minimization can be solved optimally in polynomial time. A key step in our algorithm is to compute a minimum height Kfeasible cut in a network, which is solved optimally in polynomial time based on network flow computation. Our algorithm also effectively minimizes the number of LUTs by maximizing the volume of each cut and by several post-processing operations. Based on these results, we have implemented an LUT-based FPGA mapping package called FlowMap. We have tested FlowMap on a large set of benchmark examples and compared it with other LUT-based FPGA mapping algorithms for delay optimization, including Chortle-d, MIS-pga-delay, and DAG-Map. FlowMap reduces the LUT network depth by up to 7% and reduces the number of LUTs by up to 50% compared to the three previous methods.

On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping

by Jason Cong, Yuzheng Ding - IEEE Trans. on VLSI Systems , 1994
"... In this paper we study the area and depth trade-off in LUT based FPGA technology mapping. Starting from a depth-optimal mapping solution, we perform a number of depth relaxation operations to obtain a new network with bounded increase in depth and advantageous to subsequent re-mapping for area minim ..."
Abstract - Cited by 74 (22 self) - Add to MetaCart
In this paper we study the area and depth trade-off in LUT based FPGA technology mapping. Starting from a depth-optimal mapping solution, we perform a number of depth relaxation operations to obtain a new network with bounded increase in depth and advantageous to subsequent re-mapping for area minimization. We then re-map the resulting network to obtain an area-minimized mapping solution. By gradually increasing the depth bound, for each design we are able to produce a set of mapping solutions with smooth area and depth trade-off. For the area minimization step, we have developed an optimal algorithm for computing an area-minimum mapping solution without node duplication. Experimental results show that our solution sets outperform the solutions produced by many existing mapping algorithms in terms of both area and depth minimization. 1. Introduction The Field programmable gate array (FPGA) has become a very popular technology in VLSI ASIC design and system prototyping. The lookup tabl...
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A Method for Generating Random Circuits and Its Application to Routability Measurement

by Joel Darnauer, Wayne Wei-ming Dai , 1996
"... FPLD architectures are often designed based on the results of experiments with "typical" benchmark circuits. For very large FPLDs, it may be difficult to obtain enough benchmark circuits to accurately evaluate an architecture. In this paper, we present a method for generating large random ..."
Abstract - Cited by 51 (0 self) - Add to MetaCart
FPLD architectures are often designed based on the results of experiments with "typical" benchmark circuits. For very large FPLDs, it may be difficult to obtain enough benchmark circuits to accurately evaluate an architecture. In this paper, we present a method for generating large random circuits with a fixed number of inputs, outputs, blocks, pins per cell, and approximate rent exponent. The circuits generated are used to evaluate several routability measures. We find that routability is best predicted by estimating the total wirelength in the circuit, not the mean wirelength times pins per cell. 1 The Problem of Routability Prediction 0 Routability prediction is uesful in several settings: 1) as a cost function for automatic FPLD partitioning, 2) part selection for single FPLDs, 3) FPLD architecture design, 4) FPLD comparison and characterization. FPLD synthesis usually travels through logic minimization, technology mapping, placement, routing, and delay optimization. Each of thes...

The Triptych FPGA Architecture

by Gaetano Borriello , Carl Ebeling, Scott Hauck, Steven Burns - IEEE TRANSACTIONS ON VLSI SYSTEMS , 1995
"... Field-programmable gate arrays (FPGAs) are an important implementation medium for digital logic. Unfortunately, they currently suffer from poor silicon area utilization due to routing constraints. In this paper we present Triptych, an FPGA architecture designed to achieve improved logic density wi ..."
Abstract - Cited by 34 (4 self) - Add to MetaCart
Field-programmable gate arrays (FPGAs) are an important implementation medium for digital logic. Unfortunately, they currently suffer from poor silicon area utilization due to routing constraints. In this paper we present Triptych, an FPGA architecture designed to achieve improved logic density with competitive performance. This is done by allowing a per-mapping tradeoff between logic and routing resources, and with a routing scheme designed to match the structure of typical circuits. We show that this yields a logic density improvement of up to a factor of 3.5 over commercial FPGAs, with comparable performance. We also describe Montage, the first FPGA architecture to fully support asynchronous and synchronous interface circuits.

Area and Timing Estimation for Lookup Table Based FPGAs

by Min Xu, Fadi J. Kurdahi , 1996
"... The importance of efficient area and timing estimation techniques is well-established in High-Level Synthesis (HLS), since it allows more efficient exploration of the design space while providing HLS tools with the capability of predicting the effects of technology-specifictools on the design space. ..."
Abstract - Cited by 22 (4 self) - Add to MetaCart
The importance of efficient area and timing estimation techniques is well-established in High-Level Synthesis (HLS), since it allows more efficient exploration of the design space while providing HLS tools with the capability of predicting the effects of technology-specifictools on the design space. Much of previous work has focused on estimation techniques that use very simple cost models based solely on the gate and/or literal count. Those models are not accurate enough to allow effective design space exploration since the effects of interconnect can indeed dominate the final design cost. The situation becomes even worse when the design is targeted to Field Programmable Gate Array (FPGA) technologies since the wire delay may contribute up to 60% of the overall design delay. In this paper, we present an approach of estimating area and timing for lookup table based FPGAs that takes into account not only gate area and delay but also the wiring effects. We select Xilinx XC4000 series as ...

TRIPTYCH: An FPGA Architecture with Integrated Logic and Routing

by Scott Hauck, Gaetano Borriello, Carl Ebeling - BROWN/MIT CONFERENCE ON ADVANCED RESEARCH IN VLSI AND PARALLEL SYSTEMS , 1992
"... We describe Triptych, a new FPGA architecture, that blends logic and routing resources to achieve efficient implementation of a wide range of circuits in both area and speed. The physical structure of Triptych attempts to match the structure of factored logic functions, thus providing an efficient s ..."
Abstract - Cited by 13 (5 self) - Add to MetaCart
We describe Triptych, a new FPGA architecture, that blends logic and routing resources to achieve efficient implementation of a wide range of circuits in both area and speed. The physical structure of Triptych attempts to match the structure of factored logic functions, thus providing an efficient substrate in which to implement these circuits. This approach both requires and takes advantage of an integrated approach to the mapping, placement and routing process. We first describe the Triptych architecture in detail. This is followed by the development of a new method for architectural comparison of FPGAs that is free of irrelevant implementation effects. Then the Triptych, Xilinx, Algotronix, and Concurrent Logic architectures are compared using this method to obtain normalized area and performance figures for a wide range of circuits, including both datapath elements and control logic. Our results indicate that Triptych is more area-efficient (Xilinx mappings average 3.5 times larger...

LUT-Based FPGA Technology Mapping under Arbitrary Net-Delay Models

by Jason Cong, Yuzheng Ding, Tong Gao, Kuang-chien Chen , 1994
"... The field programmable gate-array (FPGA) has become an important technology in VLSI ASIC designs. Most existing algorithms for performance-driven technology mapping for Lookup-table (LUT) based FPGA designs are based on the unit-delay model. In this paper we study the technology mapping problem unde ..."
Abstract - Cited by 8 (3 self) - Add to MetaCart
The field programmable gate-array (FPGA) has become an important technology in VLSI ASIC designs. Most existing algorithms for performance-driven technology mapping for Lookup-table (LUT) based FPGA designs are based on the unit-delay model. In this paper we study the technology mapping problem under arbitrary net-delay models. We show that if the net delay can be determined or estimated before mapping, the problem can be optimally solved in polynomial time based on efficient network flow computation. We have implemented the algorithm and tested it on a number of MCNC benchmark examples.

A Reconfigurable Approach to TCP/IP Packet Filtering

by Raymond A. Sinnappan , 2001
"... Organisations and individuals are becoming increasingly reliant on the Internet and computer networks in general. However, networks are especially prone to security risks because they allow a cracker to access potentially any resource on the network, from a remote computer anywhere in the world. ..."
Abstract - Cited by 5 (0 self) - Add to MetaCart
Organisations and individuals are becoming increasingly reliant on the Internet and computer networks in general. However, networks are especially prone to security risks because they allow a cracker to access potentially any resource on the network, from a remote computer anywhere in the world.

F.: ChipEst-FPGA: A Tool for Chip Level Area and Timing Estimation of Lookup Table Based FPGAs for High Level Applications

by Min Xu , Fadi J Kurdahi - In: Proceeding of Asia and South Pacific Design Automation Conference , 1997
"... Abstract The importance of e cient area and timing estimation techniques for hierarchical design methodology is wellestablished in High-Level Synthesis HLS, since the estimation allows more r e alistic exploration of the design space, and hierarchical design methodology matches well with HLS paradi ..."
Abstract - Cited by 3 (1 self) - Add to MetaCart
Abstract The importance of e cient area and timing estimation techniques for hierarchical design methodology is wellestablished in High-Level Synthesis HLS, since the estimation allows more r e alistic exploration of the design space, and hierarchical design methodology matches well with HLS paradigm. In this paper, we present ChipEst-FPGA, a chip level estimator for designs implemented using a hierarchical design methodology for Lookup
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Area Optimizations in FPGA Architecture and CAD

by Valavan Manohararajah , 2005
"... Field programmable gate arrays (FPGAs) are an increasingly popular implementation medium for digital circuits. An FPGA is a prefabricated piece of silicon that can be configured by the user to implement any digital circuit. This ability enables them to offer two key advantages over other implementat ..."
Abstract - Cited by 1 (1 self) - Add to MetaCart
Field programmable gate arrays (FPGAs) are an increasingly popular implementation medium for digital circuits. An FPGA is a prefabricated piece of silicon that can be configured by the user to implement any digital circuit. This ability enables them to offer two key advantages over other implementation technologies: low cost and fast time-to-market. However, the flexibility they offer comes at a steep price. Circuits implemented in FPGAs are three times slower and ten times larger than an equivalent circuit implemented using standard cells or mask programmed gate arrays. This dissertation presents area optimizations in FPGA architecture and CAD. The primary focus is on a new area efficient adaptive FPGA (AFPGA) architecture. An AFPGA is obtained from an FPGA by replacing a fraction of the configuration SRAM with adaptive SRAM whose functionality changes in response to changes in a control signal. Adaptive programmable structures (logic elements, multiplexers, and routing switches) are produced wherever adaptive SRAM is used, and the resulting structures can be shared by two subcircuits that are not required to “exist” simultaneously. To support the new architecture, a new CAD flow is proposed and a set of CAD tools