In previous work we have developed and prototyped a silicon compiler which translates a functional language (SAFL) into hardware. Here we present a SAFL-level program transformation which: (i) partitions a specification into hardware and software parts and (ii) generates a specialised architecture to execute the software part. The architecture consists of a number of interconnected heterogeneous processors. Our method allows a large design space to be explored by systematically transforming a single SAFL specification to investigate di#erent points on the area-time spectrum.

The Data Diffusion Machine (DDM) is a virtual shared memory architecture. Data items in the machine have no fixed home location but instead migrate to the processors that are actually using the data. Coherency is maintained with a hierarchical directory scheme. In an uncongested machine, all memory operations complete in a time bounded by the logarithm of the number of processors. As the machine load increases, the natural combining of the DDM hierarchy allows better network utilisation and helps maintain performance. This paper proposes an implementation of the DDM with split directories interconnected with a point-to-point network. This is easier to construct and scales better than previous designs. The paper also defines the protocol that is needed to maintain consistency on this split tree (even though the network provides a number of paths between pairs of processors). Conflictingrequests (writes on different processors to the same data item) are resolved in a time bounded by the ...

HARP1 is a circuit board designed to exploit the rigorous compilation of parallel algorithms directly into hardware. It includes a transputer closely coupled to a Field--Programmable Gate Array (FPGA). The whole system may be regarded as an instance of a process in the sense of the theory of Communicating Sequential Processes (CSP). And the major elements are also naturally viewed in the same way: both can implement many parallel communicating sub--processes. HARP1 is being used as part of a joint project between Oxford Parallel and Sharp Laboratories of Europe within the Parallel Applications Programme supported by DTI/SERC. Here it is the target of mathematical tools based upon Ruby and occam which enable unusual and novel applications to be produced and demonstrated correctly and rapidly. The design includes memory banks, a programmable frequency synthesizer and a several communication ports. The latter supports the use of parallel arrays of HARP1 boards, as well as interfacing to ...

No particular application is well-supported by a conventional microprocessor which has a predetermined set of functional units. This is particularly true in highly dynamic areas, such as multimedia, communications and other embedded systems. We suggest that additional silicon is used to provide hardware which can be dynamically configured to support any application. By combining a conventional microprocessor and FPGA reconfigurable logic on one chip, commodity pricing is maintained and yet the same part can effectively support a wide range of applications. A novel FPGA architecture is outlined which is particularly suitable for this style of implementation. Keywords : FPGA, computer architecture, parallel processing, embedded systems. Introduction Computer architecture has been a lively and relevant topic for research and development and much has changed over the fifty years or so of the history of modern computers; however, much has also remained the same. This paper explores the th...

The FLaSH (Functional Languages for Synthesising Hardware) system allows a designer to map a high level functional language, SAFL, and its more expressive extension, SAFL+, into hardware. The system has two phases: first we perform architectural exploration by applying a series of semantics-preserving transformations to SAFL specications; then the resulting specification is compiled into hardware in a resource-aware manner -- that is, we map separate functions to separate hardware functional units (functions which are called multiple times become shared functional units). This article introduces the SAFL language and shows how program transformations on it can explore area-time trade-offs. We then show how the FLaSH compiler compiles SAFL to synchronous hardware and how SAFL transformations can also express hardware/software co-design. As a case study we demonstrate how SAFL transformations allow us to rene a simple specication of a MIPS-style processor into pipelined and superscalar implementations. The superset language SAFL+ (adding process calculi features but retaining many of the design aims) is then described and given semantics both as hardware and as a programming language.

this paper who have good access to the internet may wish to note that there is a significant amount of material on the work of our group which can be accessed via the world-wide web at the address given at the end of this paper (section ??). 2 Towards a Single Framework for Systems Description

A new codesign compiler, Dash, provides a co-synthesis and co-simulation environment for mixed FPGA/processor architectures. It compiles a C-like description to a solution containing both processors and custom hardware, and allows the descriptions of FPGA-based processors to be heavily parametrised. The user may add instructions to the processors, and the Dash software architecture allows the user to add facilities for targeting these extra instructions to the compiler. This system is being used to design a number of case studies, and a single-chip codesign of an Internet video game is used to illustrate the design flow.

Digital speech processing algorithms are used in a wide variety of applications including mobile communications, digital answering machines, electronic voice mail, and personal communication services. The hardware platforms used to implement these algorithms range from special purpose Application Specific Integrated Circuits (ASICs) to more general purpose Digital Signal Processors (DSPs). Several important issues such as the design cycle, complexity, and cost, are directly impacted by the choice of a particular platform. As digital speech processing technology continues to evolve, hardware platforms that best optimise these attributes will be in very high demand. Hardware compilation, which deals with the automatic implementation of hardware/software systems from a single specification, lends itself to the investigation of these issues because essentially, it reduces the hardware design and implementation process to a purely software process. This can result in reduced cost, increased...

Introduction It has always been possible, and sometimes necessary, to create special-purpose hardware solutions to some computing problems. The prime motivation for doing this is when low-cost, general-purpose solutions, typically using microprocessors, do not have the performance required by the application. However the development of such hardware solutions is not for the faint-hearted. Development costs are usually high and timescales can be very long, making this an unattractive option where the need for high performance does not make it unavoidable. However, the emergence of Field Programmable Gate Array (FPGA) chips is rapidly changing the nature of hardware implementations, since hardware can be constructed in milliseconds by loading parametrisation data into FPGAs. If this hardware innovation is coupled with high-level tools for designing the hardware configurations, then it is possible to reduce the entire hardware design to a purely software process. Additionally, wh

This paper explores the thesis that radical changes are set to affect all aspects of computer architecture which are at least as far-reaching as any that have been witnessed in the past half-century. The force behind the changes is the newly-emerging technology of dynamically reconfigurable hardware. Dynamically Programmable Gate Array (DPGA) chips are today's most potent implementations of such hardware. Their function can be changed in milliseconds under purely software control; they are early embodiments of truly general-purpose hardware. This technology offers us the possibility of architectures which change during operation to support the current application as efficiently as possible. These reconfigurable hardware components are already being used in combination with traditional processors to deliver novel ways of implementing applications. The very fact that a combination of a processor and some reconfigurable hardware is already so useful, is a direct pointer to a future in which reconfigurable hardware finds its way inside processors and radically changes their nature, what they can do, and the ways in which we design and program them. A great deal of work has been reported on the benefits to be obtained by coupling microprocessors with Dynamically Programmable Gate Array (DPGA) components [FCC94], [ML94]. Our own work in this area was first reported in [PL91] where a modular system based on a closely-coupled 32-bit microprocessor and a DPGA was described. We have demonstrated a number of applications running in this framework including pattern matching, spell-checking, video compression and decompression, video target tracking and others [Pag95]. The success of these applications has convinced us that many applications can be run significantly faster when ther...