Results 1  10
of
14
Temperatureaware microarchitecture
 In Proceedings of the 30th Annual International Symposium on Computer Architecture
, 2003
"... With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processorlevel techniques that can regulate operating temperature when the package’s capacity is exceeded. Evaluating such techn ..."
Abstract

Cited by 469 (51 self)
 Add to MetaCart
With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processorlevel techniques that can regulate operating temperature when the package’s capacity is exceeded. Evaluating such techniques, however, requires a thermal model that is practical for architectural studies. This paper describes HotSpot, an accurate yet fast model based on an equivalent circuit of thermal resistances and capacitances that correspond to microarchitecture blocks and essential aspects of the thermal package. Validation was performed using finiteelement simulation. The paper also introduces several effective methods for dynamic thermal management (DTM): “temperaturetracking” frequency scaling, localized toggling, and migrating computation to spare hardware units. Modeling temperature at the microarchitecture level also shows that power metrics are poor predictors of temperature, and that sensor imprecision has a substantial impact on the performance of DTM. 1.
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 2005
"... Nonuniform thermal profiles on the substrate in highperformance ICs can significantly impact the performance of global onchip interconnects. This paper presents a detailed modeling and analysis of the interconnect performance degradation due to the nonuniform temperature profiles that are encoun ..."
Abstract

Cited by 57 (4 self)
 Add to MetaCart
(Show Context)
Nonuniform thermal profiles on the substrate in highperformance ICs can significantly impact the performance of global onchip interconnects. This paper presents a detailed modeling and analysis of the interconnect performance degradation due to the nonuniform temperature profiles that are encountered along long metal interconnects as a result of existing thermal gradients in the underlying Silicon substrate. A nonuniform temperaturedependent distributed RC interconnect delay model is proposed. The model is applied to a wide variety of interconnect layouts and substrate temperature distributions to quantify the impact of such thermal nonuniformities on signal integrity issues including speed degradation in global interconnect lines and skew fluctuations in clock signal distribution networks. Subsequently, a new thermally dependent zeroskew clock routing methodology is presented. This study suggests that thermallyaware analysis should become an integrated part of the various optimization steps in physicalsynthesis flow to improve the performance and integrity of signals in global ULSI interconnects.
On thermal effects in deep submicron VLSI interconnects. Design Automation Conference
, 1999
"... This paper presents a comprehensive analysis of the thermal effects in advanced high performance interconnect systems arising due to selfheating under various circuit conditions, including electrostatic discharge. Technology (Cu, lowk etc) and scaling effects on the thermal characteristics of the ..."
Abstract

Cited by 48 (10 self)
 Add to MetaCart
(Show Context)
This paper presents a comprehensive analysis of the thermal effects in advanced high performance interconnect systems arising due to selfheating under various circuit conditions, including electrostatic discharge. Technology (Cu, lowk etc) and scaling effects on the thermal characteristics of the interconnects, and on their electromigration reliability has been analyzed simultaneously, which will have important implications for providing robust and aggressive deep submicron interconnect design guidelines. Furthermore, the impact of these thermal effects on the design (driver sizing) and optimization of the interconnect length between repeaters at the upperlevel signal lines are investigated. 1
Compact modeling and spicebased simulation for electrothermal analysis of multilevel ulsi interconnects
 In Proc. Int. Conf. on Computer Aided Design
"... This paper presents both compact analytical models and fast SPICE based 3D electrothermal simulation methodology to characterize thermal effects due to Joule heating in high performance Cu/lowk interconnects under steadystate and transient stress conditions. The results demonstrate excellent agr ..."
Abstract

Cited by 25 (0 self)
 Add to MetaCart
(Show Context)
This paper presents both compact analytical models and fast SPICE based 3D electrothermal simulation methodology to characterize thermal effects due to Joule heating in high performance Cu/lowk interconnects under steadystate and transient stress conditions. The results demonstrate excellent agreement with experimental data and those using Finite Element (FE) thermal simulations (ANSYS). The effect of vias, as additional heat sinking paths to alleviate the temp erature rise in the metal wires, is included in our analysis to provide more accurate and realistic thermal diagnosis. It shows that the effectiveness of vias in reducing the temperature rise in interconnects is highly dependent on the via separation and the dielectric materials used. The analytical model is then applied to estimate the temperature distribution in multilevel interconnects. In addition, we discuss the possibility that, under the impact of thermal effects, the performance improvement expected from the use of lowk dielectric materials may be degraded. Furthermore, thermal coupling between wires is evaluated and found to be significant. Finally, the impact of metal wire aspect ratio on interconnect thermal characteristics is discussed. 1.
Analysis of substrate thermal gradient effects on optimal buffer insertion
 In ICCAD
, 2001
"... Abstract. This paper studies the effects of the substrate thermal gradients on the buffer insertion techniques. Using a nonuniform temperaturedependent distributed RC interconnect delay model, the buffer insertion problem is analyzed and design guidelines are provided to ensure the nearoptimality o ..."
Abstract

Cited by 5 (2 self)
 Add to MetaCart
(Show Context)
Abstract. This paper studies the effects of the substrate thermal gradients on the buffer insertion techniques. Using a nonuniform temperaturedependent distributed RC interconnect delay model, the buffer insertion problem is analyzed and design guidelines are provided to ensure the nearoptimality of the signal performance in the presence of the thermal gradients. In addition, the effect of temperaturedependent driver resistance on the buffer insertion is studied. Experimental results show that neglecting thermal gradients in the substrate and the interconnect lines can result in nonoptimal solutions when using standard buffer insertion techniques and that these effects intensify with technology scaling. 1
Thermal effects in deep submicron VLSl interconnects
 IEEE Int. Symp. Quality Electronic Design
"... This paper presents a comprehensive analysis of the themal effects in advanced high performance interconnect systems arising due to selfheating under various circuit conditions, including electrostatic discharge. Technology (Cu, lowk etc) and scaling effects on the thermal characteristics of the i ..."
Abstract

Cited by 3 (1 self)
 Add to MetaCart
(Show Context)
This paper presents a comprehensive analysis of the themal effects in advanced high performance interconnect systems arising due to selfheating under various circuit conditions, including electrostatic discharge. Technology (Cu, lowk etc) and scaling effects on the thermal characteristics of the interconnects, and on their electromigration reliability has been analyzed simultaneously, which will have important implications for providing robust and aggressive deep submicron interconnect design guidelines. Furthermore, the impact of these thermal effects on the design (driver sizing) and optimization of the interconnect length between repeaters at the upperlevel signal lines are investigated. 1
Analysis of NonUniform TemperatureDependent Interconnect Performance in High Performance ICs
, 2001
"... Nonuniform temperature profiles along global interconnect lines in highperformance ICs can significantly impact the performance of these lines. This paper presents a detailed analysis and modeling of the interconnect performance degradation due to nonuniform temperature profiles that exist along ..."
Abstract

Cited by 1 (0 self)
 Add to MetaCart
(Show Context)
Nonuniform temperature profiles along global interconnect lines in highperformance ICs can significantly impact the performance of these lines. This paper presents a detailed analysis and modeling of the interconnect performance degradation due to nonuniform temperature profiles that exist along their lengths, which in turn arise due to the thermal gradients in the underlying substrate. A nonuniform temperaturedependent distributed RC interconnect delay model is proposed for the first time. The model has been applied to a wide variety of interconnect layouts and temperature distributions to quantify the impact on signal integrity issues including clock skew fluctuations.
A New Analytical Thermal Model for Multilevel ULSI Interconnects Incorporating Via Effect
, 2001
"... This paper presents a compact analytical model for estimating the temperature rise of multilevel ULSI interconnects incorporating via effect. For the first time, an analytical expression is derived for the via correction factor, h, which quantifies the effect of via separation on the effective ther ..."
Abstract
 Add to MetaCart
This paper presents a compact analytical model for estimating the temperature rise of multilevel ULSI interconnects incorporating via effect. For the first time, an analytical expression is derived for the via correction factor, h, which quantifies the effect of via separation on the effective thermal conductivity of ILD (interlayer dielectrics), k ILD,effective , with k ILD,effective = k ILD /h , where 0<h<1. Both the temperature profile along the metal lines and average temperature rise of the lines can be easily obtained using this analytical model. The predicted temperature profiles are shown to be in excellent agreement with the 3D finite element thermal simulation results. The model is then applied to estimate the temperature distribution in multilevel interconnects. Significant difference in temperature distribution and maximum temperature rise is observed between the realistic situation of heat dissipation with vias and the overly simplified case that ignores via effect.
Compact Modeling and SPICEBased Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects
 Interconnects,” in Proceedings of the International Conference on ComputerAided Design
, 2001
"... This paper presents both compact analytical models and fast SPICE based 3D electrothermal simulation methodology to characterize thermal effects due to Joule heating in high performance Cu/lowk interconnects under steadystate and transient stress conditions. The results demonstrate excellent agr ..."
Abstract
 Add to MetaCart
This paper presents both compact analytical models and fast SPICE based 3D electrothermal simulation methodology to characterize thermal effects due to Joule heating in high performance Cu/lowk interconnects under steadystate and transient stress conditions. The results demonstrate excellent agreement with experimental data and those using Finite Element (FE) thermal simulations (ANSYS). The effect of vias, as additional heat sinking paths to alleviate the temperature rise in the metal wires, is included in our analysis to provide more accurate and realistic thermal diagnosis. It shows that the effectiveness of vias in reducing the temperature rise in interconnects is highly dependent on the via separation and the dielectric materials used. The analytical model is then applied to estimate the temperature distribution in multilevel interconnects. In addition, we discuss the possibility that, under the impact of thermal effects, the performance improvement expected from the use of lowk dielectric materials may be degraded. Furthermore, thermal coupling between wires is evaluated and found to be significant. Finally, the impact of metal wire aspect ratio on interconnect thermal characteristics is discussed. 1.
Global (Interconnect) Warning
, 2001
"... r distribution and signal transmission through the interconnects due to selfheating (or Joule heating) caused by the flow of current. Current flow in a VLSI interconnect causes a power dissipation of IR 2 , where I is the current through the interconnect and R is the line resistance. Since the in ..."
Abstract
 Add to MetaCart
r distribution and signal transmission through the interconnects due to selfheating (or Joule heating) caused by the flow of current. Current flow in a VLSI interconnect causes a power dissipation of IR 2 , where I is the current through the interconnect and R is the line resistance. Since the interconnects, especially the globaltier interconnects, are far away from the substrate, which is attached to the heat sink, the heat generated due to this IR 2 power dissipation cannot be efficiently removed and therefore causes an increase in interconnect temperature. This phenomenon is referred to as Joule heating or selfheating. Even though this IR 2 power dissipation is not a major portion of the total chip power dissipation, since this power is dissipated by the interconnects, which are separated from the substrate by a dielectric that has very low thermal c