Abstract — Nanoscale computing systems show great potential but at the same time introduce new challenges not encountered in the world of conventional CMOS designs and manufacturing. For example, these systems need to work around layout and doping constraints resulting from unconventional bottom-up selfassembly, and need to cope with high manufacturing defect rates and transient faults. Unfortunately, most conventional defecttolerance techniques are not directly applicable in nanoscale systems because they have been designed for very small defect rates. In this paper, we explore built-in defect-tolerance techniques on 2-D semiconductor nanowire (NW) arrays to make designs self-healing. Our approach combines circuit and systemlevel techniques and it does not require defect map extraction, reconfigurable devices, or addressing each cross-point similar to reconfigurable approaches. We show that a defect-tolerant simple processor based on our approach would be still around 3X denser than an 18-nm CMOS version with equivalent functionality; a yield greater than 30 % is achieved despite a fabric with 14 % defective FETs. Keywords-semiconductor nanowire; defect tolerance, processor I.

Recent successes in the development and self-assembly of nanoelectronic devices suggest that the ability to manufacture dense nanofabrics is on the near horizon. However, the tremendous increase in device density of nanoelectronics will be accompanied by a substantial increase in hard and soft faults, posing a major challenge to current design methodologies and tools. In this paper we propose a novel probabilistic design paradigm for defective but reconfigurable nanofabrics. The new design goal is to devise an appropriate structural /behavioral decomposition which improves scalability by constraining the reconfiguration process, while meeting a desired probability of successful instantiation, i.e, yield. Our approach not only addresses the scalability problem in configuring dense nanofabrics subject to defects, but gives a rich framework in which critical tradeoffs among performance, yield, and per chip cost can be explored. We present a concrete instance of the approach and show extensive experimental results supporting these claims.

Manufacturing defects, power density, process variability, transient faults, bulk silicon limits, rising test costs and multibillion dollar fabrication facilities are some of the challenges facing the continued scaling of CMOS. While architectural modifications

Chemically assembled electronic nanotechnology (CAEN) is a promising alternative to CMOS-based computing. However, CAEN-based circuits are expected to have huge defect densities. To solve this problem CAEN can be used to build reconfigurable fabrics which, assuming the defects can be found, are inherently defect tolerant. In this paper, we propose a scalable testing methodology for finding defects in reconfigurable devices.

This paper explores the architectural challenges introduced by emerging bottom-up fabrication of nanoelectronic circuits. The specific nanotechnology we explore proposes patterned DNA nanostructures as a scaffold for the placement and interconnection of carbon nanotube or silicon nanorod FETs to create a limited size circuit (node). Three characteristics of this technology that significantly impact architecture are 1) limited node size, 2) random node interconnection, and 3) high defect rates. We present and evaluate an accumulator-based active network architecture that is compatible with any technology that presents these three challenges. This architecture represents an initial, unoptimized solution for understanding the implications of DNA-guide self-assembly.

Defect tolerance is an extremely important aspect in nano-scale electronics as the bottom-up selfassembly fabrication process results in a significantly higher defect density compared to conventional lithography-based process. Defect tolerance techniques are therefore essential to obtain an acceptable manufacturing yield. In this paper we investigate defect tolerance properties of a two-dimensional (2D) nano-scale crossbar, which is the basic block of various nano architectures which have been recently proposed. Various nano-wire and switch faults are studied and their impact on the routability of a crossbar are investigated. In the presence of defects, it is still possible to utilize a defective crossbar at reduced functionality, i.e. as a smaller defect-free crossbar. Simulation results for different sizes and defect densities are presented. This proposed approach can be utilized by architecture designers to determine the expected size of functional (defect-free) crossbar based on defect density information obtained from the fabrication process. 1

Producing reliable nanosystems requires effectively addressing the high defect densities projected for nanotechnologies. Defect avoidance methodologies based on reconfiguration offer a promising solution to achieve defect tolerance. The idea is to start by obtaining a defect map of the target nanofabric, and then configure the desired functionality ‘around ’ its defective components. In this paper, we argue for the suitability of memory-based computing nanofabrics, address the level of granularity at which defect mapping and configuration should be performed on such fabrics, and discuss the role of hierarchy towards controlling complexity. We then propose a novel group testing method to enable self-testing and self-configuration for appropriately architected memory-based nanofabrics. The proposed testing method is scalable and simple, in that it enables the entire fabric to be tested and configured using a relatively small number of easily configurable triple-module-redundancy (TMR) test tiles executing concurrently on different regions of the target nanofabric. Our experimental results demonstrate the effectiveness of the proposed method for a representative set of benchmark kernels.

As current silicon-based techniques fast approach their practical limits, the investigation of nanoscale electronics, devices and system architectures becomes a central research priority. It is expected that nanoarchitectures will confront devices and interconnections with high inherent defect rates, which motivates the search for new architectural paradigms. In this paper, we propose a probabilistic-based design methodology for designing nanoscale computer architectures based on Markov Random Fields (MRF). The MRF can express arbitrary logic circuits and logic operation is achieved by maximizing the probability of state configurations in the logic network. Maximizing state probability is equivalent to minimizing a form of energy that depends on neighboring nodes in the network. Once we develop a library of elementary logic components, we can link them together to build desired architectures based on the belief propagation algorithm. Belief propagation is a way of organizing the global computation of marginal belief in terms of smaller local computations. We will illustrate the proposed design methodology with some elementary logic examples. Figure 1: The principle of switching with carbon nanotubes. Tubes are joined by an attractive electric field. Molecular forces maintain the connection when the field is removed. (After Lieber [11]). 1.

Architectures built using bottom-up self-assembly of nanoelectronic devices will need to tolerate defect rates that are orders of magnitude higher than those found in current CMOS technologies. In this paper, we describe and evaluate an approach to provide defect isolation in such an architecture that consists of a large number of simple computational nodes, each of which can communicate with four neighbors on single-bit asynchronous links. Our approach does not require an external defect map, nor does it require redundancy of complex computational circuits, either of which will limit the scalability of the system. We use the reverse path forwarding broadcast routing algorithm, commonly used in wide-area networks, to map out defective nodes at startup. The algorithm guarantees two things (a) the broadcast eventually terminates and (b) all functional nodes that have a path to the broadcast source will receive it. Thus, all functional and reachable nodes are connected through a broadcast tree, resulting in defect isolation. Simulations show that, for a fail-stop model of node failure, the broadcast connects all nodes that are reachable from the source. In case of low defect rates ( ≤ 10%), the broadcast reaches more than 97% of non-defective nodes. For a network of nodes in the form of a grid, our results show that, in most cases, the time taken to complete the broadcast is proportional to the square root of the number of nodes in the system. Finally, we also present an analysis of the characteristics of the trees generated by our broadcast mechanism. 1

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