Ordered Binary-Decision Diagrams (OBDDS) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satmfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as graph algorithms on OBDD

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A small change in the input to logic synthesis may cause a large change in the output implementation. This is undesirable if a designer has some investment in the old implementation and does not want it perturbed more than necessary. We describe a method that solves this problem by reusing gates from the old implementation, and restricting synthesis to the modified portions only. 1.

Boolean unification is an algorithm to obtain the general solution of a given Boolean equation. Since the general solution provides a way to represent complete don't care sets in a functional form, Boolean unification can be a powerful method when applied to logic synthesis. In this paper we present various applications of Boolean unification to combinational logic synthesis. Three topics of combinational logic synthesis: redesign, multi-level logic minimization and minimization of Boolean relations are discussed. All these problems can be uniformly formalized as Boolean unification problems. Experimental results are also reported. 1 Introduction Boolean Unification[9, 8] is a procedure to obtain the general solution of a given Boolean equation or formula. In the field of CAD for integrated circuit design, it has been applied to logic verification and test pattern generation [11, 4] combined with logic programming. In this paper we present various applications of Boolean unification...

Field programmable gate array (FPGA) makes rapid prototyping an easier task, and is useful in many applications due to its growing speed and capacity. In this paper, we present a rectification method for look-up table type FPGA's. Instead of changing the netlist of a circuit, we only modify functionality realized by look-up tables and keep the netlist equal so that there will be no change on the delay of the circuit. We formalize the problem using characteristic functions and present a redesign method based on Boolean relation techniques. 1 Introduction Field Programmable Gate Array (FPGA) is an important technology which has recently attracted much attention due to its advantage of rapid prototyping. There has also been increasing interest in using FPGA's for low-volume production of ASIC designs. Not a few papers have been published so far on logic synthesis for FPGA's, for example, Chortle and its successors Chortle-crf and Chortle-d by Francis et al. [10, 9, 11], DAG-map by Cong ...

ed state machines Deterministic state machines 1. State machine extraction (e.g. stg_extract) 2. Eliminate conditions New constraints in ITL 4. Make product 3. Presented synthesis method Sequential circuits 5. Logic synthesis State machines Figure 3: Flow of Our Redesign Method can vary according to the variant of more(Q). So the number of generated formulas is less than the number of products of variants for more(P ) and more(Q). Since the tableau expansion generates a finite number of binary subterm diagram nodes, it generates only a finite binary subterm diagrams. When we expand all binary subterm diagrams, the expansion completes. 4 A Redesign Method for Sequential Circuits We can simply use the method which generates state machine representation from any ITL formulas as a procedure to synthesize state machines and hence sequential circuits from ITL formulas. However, we cannot handle very complex ITL formulas within a reasonable time, since the expansion time grows exponentially...

In this paper, we consider a redesign technique applicable to combinational circuits implemented with gate-array or standard-cell technology, where we rectify an existing circuit only by reconnecting gates on the circuit with all the gate types unchanged. This constraint allows us to reuse the original placement as is, thereby speeding up the total time needed for a redesign. We formulate this problem as a Boolean-constraint problem and give a BDD-based algorithm to check the feasibility of redesign. 1 Introduction Incremental synthesis is a synthesis technique which reuses existing circuits to come up with circuits satisfying new specifications. Since engineering changes arise frequently in actual design processes, the technique is of practical importance from an industrial point of view. Several synthesis techniques have already been proposed for combinational circuits [2, 3, 9, 8] and sequential circuits [1], where an additional logic is attached before and/or after an existing ci...