Results 1 - 7 of 7

At-Speed Transition Fault Testing With Low Speed Scan Enable

by Nisar Ahmed, C. P. Ravikumar - in proc. IEEE VLSI Test Symposium (VTS’05 , 2005
"... With today’s design size in millions of gates and working frequency in gigahertz range, at-speed test is crucial. The launchoff-shift method has several advantages over the launch-offcapture but imposes strict requirements on transition fault testing due to at-speed scan enable signal. A novel scan- ..."
Abstract - Cited by 10 (5 self) - Add to MetaCart
With today’s design size in millions of gates and working frequency in gigahertz range, at-speed test is crucial. The launchoff-shift method has several advantages over the launch-offcapture but imposes strict requirements on transition fault testing due to at-speed scan enable signal. A novel scan-based atspeed test is proposed which generates multiple local fast scan enable signals. The scan enable control information is encapsulated in the test data and transferred during the scan operation. A new scan cell, referred to as last transition generator (LTG), is inserted in the scan chains to generate the fast local scan enable signal. The proposed technique is robust, practiceoriented and suitable for use in an industrial flow. I.
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A Novel Delay Fault Testing Methodology Using On-Chip Low Overhead Delay Measurement Hardware at Strategic Test Points

by A. Raychowdhury, S. Ghosh, S. Bhunia, D. Ghosh, K. Roy - In European Test Symposium , 2005
"... We propose a delay fault testing methodology using on-chip delay measurement hardware. We have designed a processtolerant, low-overhead delay measurement hardware and developed an algorithm to judiciously insert the hardware at internal nodes of logic blocks. Experimental results for a set of ISCAS8 ..."
Abstract - Cited by 7 (1 self) - Add to MetaCart
We propose a delay fault testing methodology using on-chip delay measurement hardware. We have designed a processtolerant, low-overhead delay measurement hardware and developed an algorithm to judiciously insert the hardware at internal nodes of logic blocks. Experimental results for a set of ISCAS89 benchmarks show up to 16.9 % improvement in transition fault coverage and up to 10.5 % increase in the number of detected faults for segment delay fault model, with fixed test length. The reduction in test length is up to 59 % for transition fault, with fixed target coverage. The delay and area overhead due to additional DFT logic is limited to 2 % and 4 % respectively. Keywords: Transition delay fault, segment delay fault, delay measurement hardware, fault coverage. I.

Improving transition delay fault coverage using hybrid scan-based technique

by Nisar Ahmed, Mohammad Tehranipoor - in 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005 , 2005
"... This paper presents a hybrid scan-based transition delay fault test. The proposed technique controls a small subset of scan cells by launch-off-shift method and the rest by launch-off-capture method. An efficient ATPG-based controllability measurement approach is proposed to select the scan cells to ..."
Abstract - Cited by 2 (1 self) - Add to MetaCart
This paper presents a hybrid scan-based transition delay fault test. The proposed technique controls a small subset of scan cells by launch-off-shift method and the rest by launch-off-capture method. An efficient ATPG-based controllability measurement approach is proposed to select the scan cells to be controlled by launch-off-shift or launch-off-capture. In this technique, local scan enable signals are generated on-chip using two local scan enable generator cells. The cells can be inserted anywhere in a scan chain and the area overhead is negligible. The launch and capture information of scan enable signals are transferred into the scan chain during scan-in process. Our technique improves the fault coverage and reduces the pattern count and the scan enable design effort. The proposed hybrid technique is practice-oriented and implemented using current commercial ATPG tools. I.
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Low-Cost Scan Test for IEEE-1500-Based SoC

by Hyunbean Yi, Jaehoon Song, Sungju Park
"... Abstract—In this paper, a reduced-pin-count-testing technique is presented to control the IEEE-1500 wrapper through the IEEE-1149.1 TAP for scan delay test. By using only the IEEE-1149.1 TAP control pins as test-access pins and by embedding an on-chip test clock generator, low-cost automated test eq ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
Abstract—In this paper, a reduced-pin-count-testing technique is presented to control the IEEE-1500 wrapper through the IEEE-1149.1 TAP for scan delay test. By using only the IEEE-1149.1 TAP control pins as test-access pins and by embedding an on-chip test clock generator, low-cost automated test equipment (ATE) can be efficiently utilized to reduce testing costs. Experi-ments show the effectiveness of our technique in utilizing the ATE channels and scan delay testing. Index Terms—Delay test, design-for-testability (DfT), IEEE 1500, reduced pin-count test (RPCT), system-on-a-chip (SoC).
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Low-Power Test Planning for Arbitrary At-Speed Delay-Test Clock Schemes

by Christian G. Zoellin, Hans-joachim Wunderlich - 28TH IEEE VLSI TEST SYMPOSIUM , 2010
"... High delay-fault coverage requires rather sophisticated clocking schemes in test mode, which usually combine launch-on-shift and launch-on-capture strategies. These complex clocking schemes make low power test planning more difficult as initialization, justification and propagation require multiple ..."
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High delay-fault coverage requires rather sophisticated clocking schemes in test mode, which usually combine launch-on-shift and launch-on-capture strategies. These complex clocking schemes make low power test planning more difficult as initialization, justification and propagation require multiple clock cycles. This paper describes a unified method to map the sequential test planning problem to a combinational circuit representation. The combinational representation is subject to known algorithms for efficient low power built-in self-test planning. Experimental results for a set of industrial circuits show that even rather complex test clocking schemes lead to an efficient low power test plan.

ATPG and DFT Algorithms for Delay Fault Testing

by Xiao Liu , 2004
"... With ever shrinking geometries, growing metal density and increasing clock rate on chips, delay testing is becoming a necessity in industry to maintain test quality for speed-related failures. The purpose of delay testing is to verify that the circuit operates correctly at the rated speed. However, ..."
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With ever shrinking geometries, growing metal density and increasing clock rate on chips, delay testing is becoming a necessity in industry to maintain test quality for speed-related failures. The purpose of delay testing is to verify that the circuit operates correctly at the rated speed. However, functional tests for delay defects are usually unacceptable for large scale designs due to the prohibitive cost of functional test patterns and the difficulty in achieving very high fault coverage. Scanbased delay testing, which could ensure a high delay fault coverage at reasonable development cost, provides a good alternative to the at-speed functional test.

1At-Speed Transition Fault Testing With Low Speed Scan Enable

by Nisar Ahmed, C. P. Ravikumar, Mohammad Tehranipoor, Jim Plusquellic
"... With today’s design size in millions of gates and working fre-quency in gigahertz range, at-speed test is crucial. The launch-off-shift method has several advantages over the launch-off-capture but imposes strict requirements on transition fault test-ing due to at-speed scan enable signal. A novel s ..."
Abstract - Add to MetaCart
With today’s design size in millions of gates and working fre-quency in gigahertz range, at-speed test is crucial. The launch-off-shift method has several advantages over the launch-off-capture but imposes strict requirements on transition fault test-ing due to at-speed scan enable signal. A novel scan-based at-speed test is proposed which generates multiple local fast scan enable signals. The scan enable control information is encap-sulated in the test data and transferred during the scan opera-tion. A new scan cell, referred to as last transition generator (LTG), is inserted in the scan chains to generate the fast local scan enable signal. The proposed technique is robust, practice-oriented and suitable for use in an industrial flow. I.
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