Results 1  10
of
46
Silicon Physical Random Functions
 In Proceedings of the Computer and Communication Security Conference
, 2002
"... We describe the notion of a Physical Random Function (PUF). ..."
Abstract

Cited by 164 (20 self)
 Add to MetaCart
(Show Context)
We describe the notion of a Physical Random Function (PUF).
Controlled physical random functions
 In Proceedings of the 18th Annual Computer Security Conference
, 2002
"... A Physical Random Function (PUF) is a random function that can only be evaluated with the help of a complex physical system. We introduce Controlled Physical Random Functions (CPUFs) which are PUFs that can only be accessed via an algorithm that is physically bound to the PUF in an inseparable way. ..."
Abstract

Cited by 80 (14 self)
 Add to MetaCart
(Show Context)
A Physical Random Function (PUF) is a random function that can only be evaluated with the help of a complex physical system. We introduce Controlled Physical Random Functions (CPUFs) which are PUFs that can only be accessed via an algorithm that is physically bound to the PUF in an inseparable way. CPUFs can be used to establish a shared secret between a physical device and a remote user. We present protocols that make this possible in a secure and flexible way, even in the case of multiple mutually mistrusting parties. Once established, the shared secret can be used to enable a wide range of applications. We describe certified execution, where a certificate is produced that proves that a specific computation was carried out on a specific processor. Certified execution has many benefits, including protection against malicious nodes in distributed computation networks. We also briefly discuss a software licensing application. 1.
Mapping statistical process variations toward circuit performance variability: an analytical modeling approach
 In Proceedings of the 42nd Annual Conference on Design Automation
"... A physical yet compact gate delay model is developed integrating shortchannel effects and the Alphapower law based timing model. This analytical approach accurately predicts both nominal delay and delay variability over a wide range of bias conditions, including subthreshold. Excellent model scal ..."
Abstract

Cited by 39 (0 self)
 Add to MetaCart
(Show Context)
A physical yet compact gate delay model is developed integrating shortchannel effects and the Alphapower law based timing model. This analytical approach accurately predicts both nominal delay and delay variability over a wide range of bias conditions, including subthreshold. Excellent model scalability enables efficient mapping between process variations and delay variability at the circuit level. Based on this model, relative importance of physical effects on delay variability has been identified. While effective channel length variation is the leading source for variability at current 90nm node, performance variability is actually more sensitive to threshold variation at the subthreshold region. Furthermore, this model is applied to investigate the limitation of low power design techniques in the presence of process variations, particularly dual Vth and L biasing. Due to excessive variability under low VDD, these techniques become ineffective.
Stochastic analysis of interconnect performance in the presence of process variations
 in Proc. Int. Conf. on Computer Aided Design (ICCAD), Nov 2004
, 2004
"... Deformations in interconnect due to process variations can lead to significant performance degradation in deep submicron circuits. Timing analyzers attempt to capture the effects of variation on delay with simplified models. The timing verification of RC or RLC networks requires the substitution of ..."
Abstract

Cited by 29 (1 self)
 Add to MetaCart
(Show Context)
Deformations in interconnect due to process variations can lead to significant performance degradation in deep submicron circuits. Timing analyzers attempt to capture the effects of variation on delay with simplified models. The timing verification of RC or RLC networks requires the substitution of such simplified models with spatial stochastic processes that capture the random nature of process variations. The present work proposes a new and viable method to compute the stochastic response of interconnects. The technique models the stochastic response in an infinite dimensional Hilbert space in terms of orthogonal polynomial expansions. A finite representation is obtained by using the Galerkin approach of minimizing the Hilbert space norm of the residual error. The key advance of the proposed method is that it provides a functional representation of the response of the system in terms of the random variables that represent the process variations. The proposed algorithm has been implemented in a procedure called OPERA. Results from OPERA simulations on commercial design test cases match well with those from the classical Monte Carlo SPICE simulations and from perturbation methods. Additionally OPERA shows good computational efficiency: speedup factor of 60 has been observed over Monte Carlo SPICE simulations.
DelayBased Circuit Authentication and Applications
 Proceedings of the 2003 ACM symposium on Applied computing
, 2003
"... We describe a technique to reliably identify individual integrated circuits (ICs), based on a prior delay characterization of the IC. ..."
Abstract

Cited by 18 (1 self)
 Add to MetaCart
(Show Context)
We describe a technique to reliably identify individual integrated circuits (ICs), based on a prior delay characterization of the IC.
A multiple level network approach for clock skew minimization with process variations
 In ASPDAC ’04: Proceedings of the 2004 conference on Asia South Pacific design automation
, 2004
"... Abstract In this paper, we investigate the effect of multilevel network for clock skew. We first define the simplified RC circuit model of a hybrid clock mesh/tree structure. The skew reduction effect of shunt segment contributed by the mesh is derived analytically from the simplified model. The re ..."
Abstract

Cited by 12 (0 self)
 Add to MetaCart
(Show Context)
Abstract In this paper, we investigate the effect of multilevel network for clock skew. We first define the simplified RC circuit model of a hybrid clock mesh/tree structure. The skew reduction effect of shunt segment contributed by the mesh is derived analytically from the simplified model. The result indicates that the skew decreases proportionally to the exponential ofR 1/R, where R 1 is the driving resistance of a leaf node in the clock tree and R is the resistance of a mesh segment. Based on our analysis, we propose a hybrid multilevel mesh and tree structure for global clock distribution. A simple optimization scheme is adopted to optimize the routing resource distribution of the multilevel mesh. Experimental results show that by adding a mesh to the bottomlevel leaves of an Htree, the clock skew can be reduced from 29.2 ps to 8.7 ps, and the multilevel networks with same total routing area can further reduce the clock skew by another 30%. We also discuss the inductive effect of mesh in the appendix. When the clock frequency is less than 4 GHz, our RC model remains valid for clock meshes with grounded shielding or using differential signals. 1.
Improved Ring Oscillator PUF: An FPGAfriendly Secure Primitive
 Journal of Cryptology
"... Abstract. In this paper, we analyze ring oscillator (RO) based physical unclonable function (PUF) on FPGAs. We show that the systematic process variation adversely affects the ability of the ROPUF to generate unique chipsignatures, and propose a compensation method to mitigate it. Moreover, a conf ..."
Abstract

Cited by 10 (0 self)
 Add to MetaCart
(Show Context)
Abstract. In this paper, we analyze ring oscillator (RO) based physical unclonable function (PUF) on FPGAs. We show that the systematic process variation adversely affects the ability of the ROPUF to generate unique chipsignatures, and propose a compensation method to mitigate it. Moreover, a configurable ring oscillator (CRO) technique is proposed to reduce noise in PUF responses. Our compensation method could improve the uniqueness of the PUF by an amount as high as 18%. The CRO technique could produce nearly 100 % errorfree PUF outputs over varying environmental conditions without postprocessing while consuming minimum area.
Stochastic testing method for transistorlevel uncertainty quantification based on generalized polynomial chaos
 IEEE Trans. ComputerAided Design Integr. Circuits Syst
, 2013
"... ar ..."
Intervalbased Robust Statistical Techniques for Nonnegative Convex Functions, with Application to Timing Analysis of Computer Chips
 Proceedings of the Second International Workshop on Reliable Engineering Computing
, 2006
"... In chip design, one of the main objectives is to decrease its clock cycle. On the design stage, this time is usually estimated by using worstcase (interval) techniques, in which we only use the bounds on the parameters that lead to delays. This analysis does not take into account that the probabili ..."
Abstract

Cited by 9 (2 self)
 Add to MetaCart
(Show Context)
In chip design, one of the main objectives is to decrease its clock cycle. On the design stage, this time is usually estimated by using worstcase (interval) techniques, in which we only use the bounds on the parameters that lead to delays. This analysis does not take into account that the probability of the worstcase values is usually very small; thus, the resulting estimates are overconservative, leading to unnecessary overdesign and underperformance of circuits. If we knew the exact probability distributions of the corresponding parameters, then we could use MonteCarlo simulations (or the corresponding analytical techniques) to get the desired estimates. In practice, however, we only have partial information about the corresponding distributions, and we want to produce estimates that are valid for all distributions which are consistent with this information.
Modeling the Effects of Systematic Process Variation on Circuit Performance
 in PhD thesis, EECS, MIT
, 2001
"... As technology scales, understanding semiconductor manufacturing variation becomes essential to effectively design high performance circuits. Knowledge of process variation is important to optimize critical path delay, minimize clock skew, and reduce crosstalk noise. Conventional circuit techniques t ..."
Abstract

Cited by 8 (0 self)
 Add to MetaCart
(Show Context)
As technology scales, understanding semiconductor manufacturing variation becomes essential to effectively design high performance circuits. Knowledge of process variation is important to optimize critical path delay, minimize clock skew, and reduce crosstalk noise. Conventional circuit techniques typically represent the interconnect and device parameter variations as random variables. However, recent studies have shown that strong spatial pattern dependencies exist, especially when considering interconnect variation in chemical mechanical polishing (CMP) processes. Therefore, the total variation can be separated into systematic and random components, where a significant portion of the variation can be modeled based on layout characteristics. Modeling the systematic components of different variation sources and implementing these effects in circuit simulation are key to reduce design uncertainty and maximize circuit performance. This thesis presents a methodology to incorporate systematic pattern dependent interconnect