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13
VLSI cell placement techniques
 ACM Computing Surveys
, 1991
"... VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive survey of the various cell placement techniques, with emphasi ..."
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Cited by 93 (0 self)
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VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive survey of the various cell placement techniques, with emphasis on standard ce11and macro
A general greedy channel routing algorithm
 IEEE TRANS. CAD
, 1991
"... This paper presents a new channel routing algorithm which assigns wires track by track in a greedy way. The simple underlying data structures and strategy used in this algorithm can be generalized to obtain a class of heuristic channel routing algorithms. The proposed new algorithm has a backtracki ..."
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Cited by 6 (1 self)
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This paper presents a new channel routing algorithm which assigns wires track by track in a greedy way. The simple underlying data structures and strategy used in this algorithm can be generalized to obtain a class of heuristic channel routing algorithms. The proposed new algorithm has a backtracking capability to increase the chance of completing the routing with a minimum number of tracks. Since the concepts described in this paper are general, they can be applied to other channel problems such as switchbox routing, threelayer routing, and multilayer routing, or it can be even applied to the overlap model with only a few modifications. It successfully routes both the Burstein’s difficult switchbox problem and Deutsch’s difficult example with 19 tracks in the Manhattan model without any backtracking. The extensions of this algorithm are presented with examples.
Simulated Annealing with Inaccurate Cost Functions
 in Proceedings of the IMACS International Congress of Mathematics and Computer Science
, 1994
"... . Simulated annealing is an algorithm which generates nearoptimal outcomes to combinatorial optimization problems. It is commonly thought to be slow. Costfunction approximation and parallel processing increase simulated annealing speed, but they can cause inaccuracies that degrade the outcome. Pri ..."
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Cited by 5 (1 self)
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. Simulated annealing is an algorithm which generates nearoptimal outcomes to combinatorial optimization problems. It is commonly thought to be slow. Costfunction approximation and parallel processing increase simulated annealing speed, but they can cause inaccuracies that degrade the outcome. Prior theoretical work has not adequately related costfunction inaccuracy to the runtime or quality of the outcome. We prove these results about annealing with inaccurate costfunctions: 1) Expected cost at equilibrium is exponentially affected by fl=T , where fl limits costfunction rangeerrors and T gives the temperature. 2) Expected cost at equilibrium is exponentially affected by (oe 2 \Gamma oe 2 )=2T 2 , when the errors have a Gaussian distribution. 3) Constraining fl to a constant factor of T guarantees convergence under a 1= log t temperature schedule. 4) A similar constraint guarantees convergence for a fractal space with a geometric temperature schedule. 5) Inaccuracies worse...
KnowledgeBased Feature Generation for Inductive Learning
, 1993
"... Inductive learning is an approach to machine learning in which concepts are learned from examples and counterexamples. One requirement for inductive learning is an explicit representation of the characteristics, or features, that determine whether an object is an example or counterexample. Obvious o ..."
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Cited by 4 (0 self)
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Inductive learning is an approach to machine learning in which concepts are learned from examples and counterexamples. One requirement for inductive learning is an explicit representation of the characteristics, or features, that determine whether an object is an example or counterexample. Obvious or easily available representations do not reliably satisfy this requirement, so constructive induction algorithms have been developed to satisfy it automatically. However, there are some features, known to be useful, that have been beyond the capabilities of most constructive induction algorithms. This diss
Architecture Evaluator's Work Bench and and its Application to Microprocessor Floating Point Units
, 1995
"... This paper introduces Architecture Evaluator's Workbench(AEWB), a high level design space exploration methodology, and its application to floating point units(FPUs). In applying AEWB to FPUs, a metric for optimizing and comparing floating point unit implementation is developed. The metric  FU ..."
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Cited by 2 (2 self)
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This paper introduces Architecture Evaluator's Workbench(AEWB), a high level design space exploration methodology, and its application to floating point units(FPUs). In applying AEWB to FPUs, a metric for optimizing and comparing floating point unit implementation is developed. The metric  FUPA incorporates four aspects of AEWB  latency, cost, technology and profiles of target applications. FUPA models latency in terms of delay, cost in terms of area, and profile in terms of percentage of different floating point operations. We utilize submicron device models, interconnect models, and actual microprocessor scaling data to develop models used to normalize both latency and area enabling technologyindependent comparison of implementations. This report also surveyed most of the state of the art microprocessors, and compared them utilizing FUPA. Finally, we correlate the FUPA results to reported SPECfp92 results, and demonstrate the effect of circuit density on FUPA implementations. ...
An Integer Programming Approach to Placement and Routing in Circuit Layout
"... A circuit layout problem requires determining the component pin placement and routing of interconnections for a given circuit schematic on a single or multilayer printed circuit board. In this paper, an integer programming based approach is introduced to solve the layout problem which performs place ..."
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A circuit layout problem requires determining the component pin placement and routing of interconnections for a given circuit schematic on a single or multilayer printed circuit board. In this paper, an integer programming based approach is introduced to solve the layout problem which performs placement and routing simultaneously. Since an integer programming problem is computationally intractable, a heuristic method to solve the placement and routing separately has been developed by utilizing the integer programming formulation. By applying a fixed routing scheme that connects components by direct line segments, the layout problem is transformed into a quadratic cost optimization problem in which the only decision variable is the pin placement, and which is solved by drawing an analogy between the quadratic cost term and the power dissipation term in a purely resistive network. Partitioning is then used to assign components to locations on a grid. Once the placement is determined, rou...
Acceleration of FPGA placement
, 2005
"... Placement (and routing) of circuits is very computationally intensive. This intensity has motivated several attempts at acceleration of this process for applicationspecific integrated circuits (ASIC) and Fieldprogrammable gate arrays (FPGA). In this paper an overview of some of these attempts is g ..."
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Placement (and routing) of circuits is very computationally intensive. This intensity has motivated several attempts at acceleration of this process for applicationspecific integrated circuits (ASIC) and Fieldprogrammable gate arrays (FPGA). In this paper an overview of some of these attempts is given. Specifically, parallelization of the standard simulated annealing (SA) algorithm is examined as well as a particular improvement to VPR, the academic Versatile Place and Route tool. Overall, it is clear that SA is difficult to parallelize and that very minor improvements on a wellknown tool is cause for publication. A discussion is provided outlining a more innovative and potentially fruitful direction for acceleration of placement and routing. 1 Introduction and
Acceleration of FPGA placement
, 2005
"... 1 Introduction and motivation FPGAs are circuits that can be programmed (and reprogrammed) in the field. Logic functions are typically implemented with lookup tables and flipflops. The routing between the various blocks is also programmable with the ability to connect the output of virtually any l ..."
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1 Introduction and motivation FPGAs are circuits that can be programmed (and reprogrammed) in the field. Logic functions are typically implemented with lookup tables and flipflops. The routing between the various blocks is also programmable with the ability to connect the output of virtually any logic block with any other. Through synthesis of a hardwaredescription language like Verilog or VHDL, user logic is mapped to these logic blocks. After this mapping, it is necessary to make decisions as to the physical location of these logic blocks and which routing resources should be dedicated to which nets. To perform this placement and routing in an optimal manner is a proven NPcomplete problem [1]. There are several methods for providing solutions that are acceptable to the designer in a tractable amount of time. Some of these include simulated annealing (SA), forcedirected placement, mincut placement, placement by numerical optimization, and evolutionbased placement[2]. In this paper, we are mostly concerned with SA, though evolutionary techniques will make a brief appearance.
Abstract Managing Circuit Don’t Cares in Boolean Satisfiability
"... Boolean Satisfiability solvers are widely used in many VLSI Computer Aided Design applications. Their popularity is due to recent developments such as effective search space pruning, decision making, and learning from previous mistakes. Most SAT algorithms and performance improvement techniques foc ..."
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Boolean Satisfiability solvers are widely used in many VLSI Computer Aided Design applications. Their popularity is due to recent developments such as effective search space pruning, decision making, and learning from previous mistakes. Most SAT algorithms and performance improvement techniques focus on the core engine and do not exploit circuit specific properties. Historically, properties such as don’t care conditions have played an important role in problems such as test pattern generation and circuit synthesis. This thesis presents a number of techniques that increase SAT solver performance by taking advantage of circuit don’t care conditions. General strategies and specific heuristics are developed that utilize a circuit’s observability don’t cares, controllability don’t cares, and don’t care states to improve SAT solver efficiency for formal verification problems. Extensive experiments demonstrate the benefits of don’t care conditions on benchmark suites as well as industrial circuits. ii Acknowledgements First and foremost I would like to thank Professor Andreas Veneris for his endless patience and invaluable advice without which this thesis could not be possible. I am very grateful for