Abstract—In this paper we present an efficient heuristic algorithm for the post-layout layer assignment and via minimization £ problem of multilayer gridless integrated circuit (IC), printed ¤ circuit board (PCB), and multichip module (MCM) layouts. We formulate the multilayer layer assignment problem by introduc-ing the notion of the extended conflict-continuation (ECC) graph. When the formulated ECC graph of a layer assignment problem is a tree, we show that the problem can be solved by an algorithm § which is both linear time and optimal. When the formulated ECC ¨graph is not a tree, we present an algorithm which constructs © a sequence of maximal induced subtrees from the ECC graph, then applies our linear time optimal algorithm to each of the induced subtrees to refine the layer assignment. Our experiments

An important problem in performance-driven routing is the k -layer planar subset problem which is to choose a maximum (weighted) subset of nets such that each net in the subset can be routed in one of k "preferred" layers. Related to the k -layer planar subset problem is the k -layer topological via-minimization problem which is to determine the topology of each net using k routing layers such that a minimum number of vias is used. For the case k = 2, the topological via minimization problem has been studied by CAD researchers for a long time because of its practical and theoretical importance. In this paper, we show that both the general k -layer planar subset problem and the k -layer topological via minimization problem are NP-complete. Moreover, we show that both problems can be solved in polynomial time when the routing regions are crossing channels. It can be shown that under a suitable assumption, all the channels for inter-block connections in the general cell design style are ...

In this thesis, we explore three problems arising during the logic syn-thesis and physical design stages of VLSI circuit design. We rst present a new formulation for the retiming of single-phase clocked circuits containing latches. Then, we discuss crosstalk optimization in channel-based routings, and nally present a new performance-driven algorithm for the layer assign-ment of critical global nets. Although single-phase clocked circuits containing latches are in widespread use, there is no existing practical formulation for such circuits that allows retiming-based optimizations. We present anovel, ILP-based formulation for the retiming of such circuits. This formulation can be used to optimize any linearizable objective function. As examples, we discuss the optimiza-tion of the clock period and the area of such circuits. Our experiments demonstrate that our approach ise cient and generates ILPs that are easy to solve. We address the increased importance of crosstalk avoidance in deep sub-