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36
"It’s a small world after all": NoC performance optimization via long-range link insertion
- IEEE TRANS. VERY LARGE SCALE INTEGRATION SYSTEMS
, 2006
"... Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an archi ..."
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Cited by 62 (8 self)
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Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture which is neither regular nor fully customized. Instead, the communication architecture we propose is a superposition of a few long-range links and a standard mesh network. The few application-specific long-range links we insert significantly increase the critical traffic workload at which the network transitions from a free to a congested state. This way, we can exploit the benefits offered by both complete regularity and partial topology customization. Indeed, our experimental results demonstrate a significant reduction in the average packet latency and a major improvement in the achievable network through with minimal impact on network topology.
Outstanding Research Problems in NoC Design: Circuit-, Microarchitecture-, and System-Level Perspectives
"... Abstract—Networks-on-Chip (NoCs) have been recently proposed to replace global interconnects in order to alleviate complex communication problems. While several research problems concerning NoC design have been already addressed in the literature, many others remain to be solved. In this work, we fi ..."
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Cited by 52 (1 self)
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Abstract—Networks-on-Chip (NoCs) have been recently proposed to replace global interconnects in order to alleviate complex communication problems. While several research problems concerning NoC design have been already addressed in the literature, many others remain to be solved. In this work, we first provide a general description of NoC architectures and applications. Then, we enumerate several related research problems organized under five main categories: Application characterization, communication paradigm, communication infrastructure, analysis and solution evaluation. Motivation, problem formulation, proposed approaches and open issues are discussed for each problem enumerated in the paper from circuit, micro-architecture and systemlevel perspectives. Finally, we address the interactions among these research problems and put the NoC design process into perspective. Index terms — On-chip communication architecture, networks-onchip, multiprocessor system-on-chip, CMP. I.
Key Research Problems in NoC Design: A Holistic Perspective
- in Proc. of the Int’l Conf. on HW-SW Codesign and System Synthesis
, 2005
"... Networks-on-Chip (NoCs) have been recently proposed as a promising solution to complex on-chip communication problems. The lack of an unified representation of applications and architectures makes NoC problem formulation and classification both difficult and obscure. To remedy this situation, we pro ..."
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Cited by 45 (7 self)
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Networks-on-Chip (NoCs) have been recently proposed as a promising solution to complex on-chip communication problems. The lack of an unified representation of applications and architectures makes NoC problem formulation and classification both difficult and obscure. To remedy this situation, we provide a general description for NoC architectures and applications and then enumerate several outstanding research problems (denoted by P1-P8) organized under three topics: communication infrastructure synthesis, communication paradigm selection, and application mapping optimization. Far from being exhaustive, the discussed problems are deemed essential for future NoC research.
An Application-Specific Design Methodology for On-Chip Crossbar Generation
- IEEE Trans. on CAD
, 2007
"... As the communication requirements of current and future Multiprocessor Systems on Chips (MPSoCs) continue to in-crease, scalable communication architectures are needed to support the heavy communication demands of the system. This is reflected in the recent trend that many of the stan-dard bus produ ..."
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Cited by 41 (5 self)
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As the communication requirements of current and future Multiprocessor Systems on Chips (MPSoCs) continue to in-crease, scalable communication architectures are needed to support the heavy communication demands of the system. This is reflected in the recent trend that many of the stan-dard bus products such as STbus, have now introduced the capability of designing a crossbar with multiple buses oper-ating in parallel. The crossbar configuration should be de-signed to closely match the application traffic characteris-tics and performance requirements. In this work we address this issue of application-specific design of optimal crossbar (using STbus crossbar architecture), satisfying the perfor-mance requirements of the application and optimal binding of cores onto the crossbar resources. We present a simula-tion based design approach that is based on analysis of ac-tual traffic trace of the application, considering local varia-tions in traffic rates, temporal overlap among traffic streams and criticality of traffic streams. Our methodology is ap-plied to several MPSoC designs and the resulting crossbar platforms are validated for performance by cycle-accurate SystemC simulation of the designs. The experimental case studies show large reduction in packet latencies (up to 7×) and large crossbar component savings (up to 3.5×) com-pared to traditional design approaches.
Energy- and performancedriven NoC communication architectures synthesis using a decomposition approach
- in Proc. Design, Automation & Test in Europe Conf
, 2005
"... In this paper, we present a methodology for customized communication architecture synthesis that matches the com-munication requirements of the target application. This is an important problem, particularly for network-based implemen-tations of complex applications. Our approach is based on using fr ..."
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Cited by 32 (4 self)
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In this paper, we present a methodology for customized communication architecture synthesis that matches the com-munication requirements of the target application. This is an important problem, particularly for network-based implemen-tations of complex applications. Our approach is based on using frequently encountered generic communication primi-tives as an alphabet capable of characterizing any given com-munication pattern. The proposed algorithm searches through the entire design space for a solution that minimizes the system total energy consumption, while satisfying the other design constraints. Compared to the standard mesh architecture, the customized architecture generated by the newly proposed approach shows about 36 % throughput increase and 51 % reduction in the energy required to encrypt 128 bits of data with a standard encryption algorithm. 1.
Linear-programmingbased techniques for synthesis of network-on-chip architectures
- IEEE Trans. Very Large Scale Integr. Syst
, 2006
"... offers the opportunity for incorporating custom network-on-chip (NoC) architectures that are more suitable for a particular appli-cation, and do not necessarily conform to regular topologies. This paper presents novel mixed integer linear programming (MILP) formulations for synthesis of custom NoC a ..."
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Cited by 30 (1 self)
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offers the opportunity for incorporating custom network-on-chip (NoC) architectures that are more suitable for a particular appli-cation, and do not necessarily conform to regular topologies. This paper presents novel mixed integer linear programming (MILP) formulations for synthesis of custom NoC architectures. The optimization objective of the techniques is to minimize the power consumption subject to the performance constraints. We present a two-stage approach for solving the custom NoC synthesis problem. The power consumption of the NoC architecture is determined by both the physical links and routers. The power consumption of a physical link is dependent upon the length of the link, which in turn, is governed by the layout of the SoC. Therefore, in the first stage, we address the floorplanning problem that determines the locations of the various cores and the routers. In the second stage, we utilize the floorplan from the first stage to generate topology of the NoC and the routes for the various traffic traces. We also present a clustering-based heuristic technique for the second stage to reduce the run times of the MILP formulation. We analyze the quality of the results and solution times of the proposed techniques by extensive experimentation with realistic benchmarks and comparisons with regular mesh-based NoC architectures. Index Terms—Design automation, integrated circuit intercon-nection, multiprocessor interconnection. I.
An automated technique for topology and route generation of application specific on-chip interconnection networks
- in Proc. ICCAD, 2005
"... Abstract — Network-on-chip (NoC)) has been proposed as a solution to the communication challenges of System-on-chip (SoC) design in nanoscale technologies. Application specific SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular applic ..."
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Cited by 28 (1 self)
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Abstract — Network-on-chip (NoC)) has been proposed as a solution to the communication challenges of System-on-chip (SoC) design in nanoscale technologies. Application specific SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. Custom NoC design in nanoscale technologies must address performance requirements, power consumption and physical layout consider-ations. This paper presents a novel three phase technique that i) generates a performance aware layout of the SoC, ii) maps the cores of the SoC to routers, and iii) generates a unique route for every trace that satisfies the performance and architectural constraints. We present an analysis of the quality of the results of the proposed technique by experimentation with realistic benchmarks. I.
Undisrupted Quality-ofService during Reconfiguration of Multiple Applications in Networks on Chip
- In Proc. DATE 2007
"... Abstract Networks on Chip (NoC) have emerged as the design paradigm for scalable System on Chip (SoC) communication infrastructure. Due to convergence, a growing number of applications are integrated on the same chip. When combined, these applications result in use-cases with different communicatio ..."
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Cited by 22 (7 self)
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Abstract Networks on Chip (NoC) have emerged as the design paradigm for scalable System on Chip (SoC) communication infrastructure. Due to convergence, a growing number of applications are integrated on the same chip. When combined, these applications result in use-cases with different communication requirements. The NoC is configured per use-case and traditionally all running applications are disrupted during use-case transitions, even those continuing operation. In this paper we present a model that enables partial reconfiguration of NoCs and a mapping algorithm that uses the model to map multiple applications onto a NoC with undisrupted Quality-of-Service during reconfiguration. The performance of the methodology is verified by comparison with existing solutions for several SoC designs. We apply the algorithm to a mobile phone SoC with telecom, multimedia and gaming applications, reducing NoC area by more than 17% and power consumption by 50% compared to a state-of-the-art approach.
SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chips
- in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, 2010
"... Abstract—Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs). Designing an efficient network on chip (NoC) interconnect for a 3-D SoC that meets not only the application performance constraints but als ..."
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Cited by 21 (6 self)
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Abstract—Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs). Designing an efficient network on chip (NoC) interconnect for a 3-D SoC that meets not only the application performance constraints but also the constraints imposed by the 3-D technology is a significant challenge. In this paper, we present a design tool, SunFloor 3D, to synthesize application-specific 3-D NoCs. The proposed tool determines the best NoC topology for the application, finds paths for the communication flows, assigns the network components to the 3-D layers, and places them in each layer. We perform experiments on several SoC benchmarks and present a comparative study between 3-D and 2-D NoC designs. Our studies show large improvements in interconnect power consumption (average of 38%) and delay (average of 13%) for the 3-D NoC when compared to the corresponding 2-D implementation. Our studies also show that the synthesized topologies result in large power (average of 54%) and delay savings (average of 21%) when compared to standard topologies. Index Terms—3-D integrated circuits (3D-ICs), networks on chip (NoC), placement, synthesis, topology. I.
System level design paradigms: Platform-based design and communication synthesis
- ACM Trans. Des. Autom. Electron. Syst
, 2006
"... Embedded system level design must be based on paradigms that make formal foundations and unification a cornerstone of their construction. Platform-Based designs and communication synthesis are important components of the paradigm shift we advocate. Communication synthesis is a fundamental productivi ..."
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Cited by 10 (3 self)
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Embedded system level design must be based on paradigms that make formal foundations and unification a cornerstone of their construction. Platform-Based designs and communication synthesis are important components of the paradigm shift we advocate. Communication synthesis is a fundamental productivity tool in a design methodology where reuse is enforced. Communication design in a reuse methodology starts with a set of functional requirements and constraints on the interaction among components and then proceeds to build protocols, topology, and physical implementations that satisfy requirements and constraints while optimizing appropriate measures of efficiency of the implementation. Maximum efficiency can be reached when the communication specifications are entered at high levels of abstraction and the design process optimizes the implementation from this specification. Unfortunately, this process is very difficult if it is not cast in a rigorous framework. Platform-Based design helps define a successive refinement process where each step can be carried out automatically and optimized appropriately. We present two cases, an on-chip and a wireless sensor network design, where the resulting methodology gave encouraging results.
