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Determinate STG Decomposition of Marked Graphs ⋆
"... Abstract. STGs give a formalism for the description of asynchronous circuits based on Petri nets. To overcome the state explosion problem one may encounter during circuit synthesis, a nondeterministic algorithm for decomposing STGs was suggested by Chu and improved by one of the present authors. To ..."
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Abstract. STGs give a formalism for the description of asynchronous circuits based on Petri nets. To overcome the state explosion problem one may encounter during circuit synthesis, a nondeterministic algorithm for decomposing STGs was suggested by Chu and improved by one of the present authors. To find the best possible result the algorithm might produce, it would be important to know to what extent nondeterminism influences the result, i.e. to what extent the algorithm is determinate. The result of the algorithm clearly depends on the partition of output signals that has to be chosen initially. In general, it also depends on the order of computation steps. We prove that for live marked graphs — a subclass of Petri nets of definite practical importance in the area of circuit design — the decomposition result depends only on the signal partition. In the proof, we also characterise redundant places in these marked graphs as shortcut places; this easytoapply graphtheoretic characterisation is of independent interest. 1
Compositional Approach to Design of Digital Circuits
"... Supported by EPSRC grants EP/G037809/1 and EP/K001698/1 NCLEEEMICROTR2014191 Copyright c © 2014 University of Newcastle upon Tyne ..."
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Supported by EPSRC grants EP/G037809/1 and EP/K001698/1 NCLEEEMICROTR2014191 Copyright c © 2014 University of Newcastle upon Tyne
Efficient Automatic Resolution of Encoding Conflicts Using STG Unfoldings
, 2009
"... Synthesis of asynchronous circuits from Signal Transition Graphs (STGs) involves resolution of state encoding conflicts by means of refining the STG specification. In this paper, a fully automatic technique for resolving such conflicts by means of insertion of new signals and concurrency reduction i ..."
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Synthesis of asynchronous circuits from Signal Transition Graphs (STGs) involves resolution of state encoding conflicts by means of refining the STG specification. In this paper, a fully automatic technique for resolving such conflicts by means of insertion of new signals and concurrency reduction is proposed. It is based on conflict cores, i.e., sets of transitions causing encoding conflicts, which are represented at the level of finite and complete unfolding prefixes, and a SAT solver is used to find where in the STG the transitions of new signals should be inserted and to check the validity of concurrency reductions. The experimental results show significant improvements over the state space based approach in terms of runtime and memory consumption, as well as some improvements in the quality of the resulting circuits.
Slicing and Reduction Techniques for Model Checking Petri Nets Dissertation zur Erlangung des Grades eines
"... Ein Model Checker untersucht dann vollautomatisch, ob das Modell eine Eigenschaft erfüllt, indem er dessen Zustandsraum untersucht. Da jedoch die Anzahl der Zustände exponentiell mit der Größe des Systems wachsen kann –was als Zustandsraumexplosion bezeichnet wird – ist die Entwicklung und Anwendung ..."
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Ein Model Checker untersucht dann vollautomatisch, ob das Modell eine Eigenschaft erfüllt, indem er dessen Zustandsraum untersucht. Da jedoch die Anzahl der Zustände exponentiell mit der Größe des Systems wachsen kann –was als Zustandsraumexplosion bezeichnet wird – ist die Entwicklung und Anwendung von Methoden unumgänglich, die es ermöglichen beim Model Checking mit Systemen umzugehen, die einen großen Zustandsraum haben.
Avoiding Irreducible CSC Conflicts by Internal Communication ∗
, 2008
"... Resynthesis of handshake specifications obtained e.g. from Balsa or Tangram with speedindependent logic synthesis from STGs is a promising approach [CC06]. To deal with statespaceexplosion, we suggested STG decomposition; a problem is that decomposition can lead to irreducible CSC conflicts. Here ..."
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Resynthesis of handshake specifications obtained e.g. from Balsa or Tangram with speedindependent logic synthesis from STGs is a promising approach [CC06]. To deal with statespaceexplosion, we suggested STG decomposition; a problem is that decomposition can lead to irreducible CSC conflicts. Here, we present a new approach to solve such conflicts by introducing internal communication between the components. We give some first, very encouraging results for very large STGs concerning synthesis time and circuit area.
49.4 Decomposing Specifications with Concurrent Outputs to Resolve State Coding Conflicts in Asynchronous Logic Synthesis ABSTRACT
"... Synthesis of asynchronous logic using the tool Petrify requires a state graph with a complete state coding. It is common for specifications to exhibit concurrent outputs, but Petrify is sometimes unable to resolve the state coding conflicts that arise as a result, and hence cannot synthesise a circu ..."
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Synthesis of asynchronous logic using the tool Petrify requires a state graph with a complete state coding. It is common for specifications to exhibit concurrent outputs, but Petrify is sometimes unable to resolve the state coding conflicts that arise as a result, and hence cannot synthesise a circuit. A pair of decomposition heuristics (expressed in the language of DelayInsensitive Sequential Processes) are given that helps one to obtain a synthesisable specification. The second heuristic has been successfully applied to a set of nine benchmarks to obtain significant reductions both in area and in synthesis time, compared with synthesis performed on the original specifications. Categories and Subject Descriptors:
DESI: a Tool for Decomposing Signal Transition Graphs
"... Signal Transition Graphs (STGs) are a version of Petri nets for the specification of asynchronous circuit behaviour. As a first step in the indirect synthesis of a circuit corresponding to a given STG N, one usually constructs the ..."
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Signal Transition Graphs (STGs) are a version of Petri nets for the specification of asynchronous circuit behaviour. As a first step in the indirect synthesis of a circuit corresponding to a given STG N, one usually constructs the
A usable rechability analyser
, 2009
"... Reachability analysis consists in checking if a state satisfying some property is reachable. In this paper a solution to the problem of generating formulae expressing reachability properties for concrete models is suggested. The traditional methods either require the user to input the formula manual ..."
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Reachability analysis consists in checking if a state satisfying some property is reachable. In this paper a solution to the problem of generating formulae expressing reachability properties for concrete models is suggested. The traditional methods either require the user to input the formula manually, which can be very tedious and errorprone, or automatically generate formulae for some fixed set of common properties, which does not allow one to check custom properties. The proposed approach allows the user to write a concise abstract specification of the property in a specially developed language Reach, which is then automatically expanded into a formula for a concrete model. The usefulness of this method is demonstrated on several case studies.
DelayInsensitive Processes: A Formal Approach to the Design of Asynchronous Circuits
"... With the proliferation of electronic devices in our daytoday existence, the quality of the underlying circuits is becoming increasingly important. The devices are expected to run robustly under different operating conditions. Asynchronous circuits are promising as compared to synchronous approach, ..."
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With the proliferation of electronic devices in our daytoday existence, the quality of the underlying circuits is becoming increasingly important. The devices are expected to run robustly under different operating conditions. Asynchronous circuits are promising as compared to synchronous approach, in achieving low power, low noise and high speed circuits which can be developed in a modular way. However, the absence of a global clock in these circuits comes at the cost of added concurrency. Therefore, it is important to have a better understanding of such highly concurrent systems in order to have confidence in the resultant devices. A formalism known as delayinsensitive (DI) processes is used to reason about a special class of asynchronous circuits that make no assumptions about delays in any of its components or wires. The formalism is shown to be useful in verification of such circuits using existing verification tools. DI processes can be easily integrated into such tools and existing equivalence checking techniques applied to them, instead of starting from scratch. In particular, the application of the Concurrency