this paper, and a great deal of e#ort has been invested into researchin this #eld. This paper considers the method of retiming #1#, which proceeds by relocating #ip-#ops within a network to achieve faster clocking speeds. A novel approach to retiming that utilizes the solution of the clockskew optimization problem #2# forms the backbone of this work

Abstract not found

The introduction of clockskew at an edge-triggered flip-flop has an effect that is similar to the movement of the flip-flop across combinational logic module boundaries, and these are continuous and discrete optimizations with the same effect. While this fact has been recognized before, this work, for the first time, utilizes this information to find a minimum/specified period retiming efficiently. The clock period is guaranteed to be at most one gate delay larger than a tight lower bound on the optimal clock period; this bound is achievable using a combination of intentional skew and retiming. All ISCAS89 circuits can be retimed in a few minutes by this algorithm.

Retiming relocates registers in a circuit to shorten the clock cycle time. In deep sub-micron era, conventional pre-layout retiming cannot work properly because of dominant interconnection delay that is not available before layout. Although some retiming algorithms incorporating interconnection delay have been proposed, layout information is still not utilized e ectively nor e ciently. Retiming and layout is combined for the rst time in this paper. We present heuristics for two key problems: interconnection delay estimation and post-retiming incremental placement. An e cient retiming algorithm incorporating interconnection delay is also proposed. Experimental results show that on the average we can improve the circuit speed by 5:4 % targeted toward a0:5um CMOS technology. Scaling down the technology to 0:1um, asmuch as25:6 % improvement have been achieved. 1

The FPGA technology mapping and synthesis problem for combinational circuits has been well studied. But for sequential circuits, most of the previous synthesis and mapping algorithms assume that the positions of flipflops are fixed and synthesize each combinational block independently. Retiming is a technique to reduce the clock period by repositioning flipflops [LeSa91]. With retiming, the previous mapping algorithms may not lead to an optimal solution of a sequential circuit by mapping each combinational block independently. Pan and Liu [PaLi96b] recently proposed a novel algorithm, named SeqMapII, of technology mapping with retiming for the optimal clock period. The time complexity of their algorithm, however, is O(K 3 n 4 log(Kn 2 ) log n) for sequential circuits with n gates and targeting K-LUT based FPGAs, which is too high for medium and large size designs in practice (more than 20 hours of CPU time to get the optimal solution for a design of 134 gates on a SPARC10 worksta...

Retiming is a powerful technique for optimizing sequential circuits. The transparent nature of level sensitive latches enables level-clocked circuits to operate faster and require fewer memory elements than edge-triggered circuits. However, this transparency makes the operation of level-clocked circuits very complex, and optimization of level-clocked circuits is a difficult task. This work presents efficient algorithms for retiming large level-clocked circuits. To provide us with a simpler view of the operation of level-clocked circuits we present the relationship between retiming and clockskew optimization. We then utilize this relationship to develop efficient retiming algorithms for period and area optimization. For period optimization we present an algorithm which produces near-optimal results, but is significantly faster than the traditional algorithms. In this approach we first calculate the best possible clock period and the amount of motion required for each latch. The latches are then relocated in an attempt to achieve this period. Area, as measured by the number of latches in the circuit can be optimized, by solving a linear program. We apply efficient pruning techniques to reduce the size of this linear program, while preserving optimality. Since generating the linear program is a major part of the computational requirements of minarea retiming, we present techniques for efficient generation of the reduced linear program. This enables us to perform area optimization of large circuits clocked by symmetric multi-phase clocks in very reasonable time, without sacrificing optimality. We present results on circuits with up to 56,000 gates, performing period optimization in under 20 seconds and area optimization in under 1.5 hours.

The concept of improving the timing behavior of a circuit by relocating registers is called retiming and was first presented by Leiserson and Saxe. They showed that the problem of determining an equivalent minimum area (total number of registers) circuit is polynomial-time solvable. In this work, we show how this approach can be reapplied in the deep sub-micron domain when area-delay trade-offs and delay constraints are considered. The main result is that the concavity of the trade-off function allows for casting this problem into a classical minimum area retiming problem. The solution paves the way for retiming to be incorporated in the architectural floorplanning stage of a design flow tailored for deep sub-micron circuits. Some examples and a register-based interconnect strategy suitable to the developed retiming technique on global wires is presented.

Logic synthesis systems are complex systems and algorithmic research in synthesis has become highly specialized. This creates a gap where it is often not clear how an advance in a particular algorithm translates into a better synthesis system. This tutorial starts by describing a set of constraints which synthesis algorithms must satisfy to be useful. A small set of established techniques are reviewed relative to these criteria to understand their applicability and the potential for further research in these areas. 1 Introduction A Logic Synthesis System converts a description of a digital circuit into an interconnection of logic gates (a gate-level net-list). A circuit description is written in a hardware description language (hdl) such as vhdl or Verilog. These languages support descriptions at three basic levels: ffl gate level: An explicit interconnection of gates in a given technology is specified. ffl register-transfer level: The location of the memory elements is fixed by th...

Q uantitative M odeling I n P arallel S ystems

This paper is devoted to a low-complexity algorithm for retiming circuits without cycles, i.e. whose network graph is a Direct Acyclic Graph (DAG). On one hand DAGs have a great practical importance, as shown by the on-line arithmetic circuits used as a target application in this paper. On the other hand retiming is a costly design optimization technique, in particular when applied to large circuits. Hence the need to design a specialized retiming algorithm to handle DAGs more eciently than general-purpose retiming algorithms. Our algorithm dramatically improves on current solutions in the literature: we gain an order of magnitude in the worst-case complexity, and we show convincing experimental results at the end of the paper.