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HighLevel Power Modeling, Estimation, and Optimization
 IEEE Trans. On Computer Aided Design
, 1998
"... Abstract—Silicon area, performance, and testability have been, so far, the major design constraints to be met during the development of digital verylargescaleintegration (VLSI) systems. In recent years, however, things have changed; increasingly, power has been given weight comparable to the othe ..."
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Cited by 106 (12 self)
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Abstract—Silicon area, performance, and testability have been, so far, the major design constraints to be met during the development of digital verylargescaleintegration (VLSI) systems. In recent years, however, things have changed; increasingly, power has been given weight comparable to the other design parameters. This is primarily due to the remarkable success of personal computing devices and wireless communication systems, which demand highspeed computations with low power consumption. In addition, there exists a strong pressure for manufacturers of highend products to keep power under control, due to the increased costs of packaging and cooling this type of devices. Last, the need of ensuring high circuit reliability has turned out to be more stringent. The availability of tools for the automatic design of lowpower VLSI systems has thus become necessary. More specifically, following a natural trend, the interests of the researchers have lately shifted to the investigation of power modeling, estimation, synthesis, and optimization techniques that account for power dissipation during the early stages of the design flow. This paper surveys representative contributions to this area that have appeared in the recent literature. Index Terms — Behavioral and logic synthesis, low power design, power management. I.
CycleAccurate MacroModels for RTLevel Power Analysis
 IEEE Trans. VLSI Systems
, 1997
"... In this paper we present a methodology and techniques for generating cycleaccurate macromodels for RTlevel power analysis. The proposed macromodel predicts not only the cyclebycycle power consumption of a module, but the power profile of the module over time. The proposed methodology consists ..."
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Cited by 48 (2 self)
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In this paper we present a methodology and techniques for generating cycleaccurate macromodels for RTlevel power analysis. The proposed macromodel predicts not only the cyclebycycle power consumption of a module, but the power profile of the module over time. The proposed methodology consists of three steps: module equation form generation and variable selection, variable reduction, and population stratification. First order temporal correlations and spatial correlations of up to order 3 are considered to improve the estimation accuracy. Experimental results show that, the macromodels have 15 or less variables and exhibit <5% error in average power, and <15% errors in cyclebycycle power compared to circuit simulation results using Powermill. I. INTRODUCTION Due to rapid progress in the semiconductor manufacturing, the device density and operating frequency have greatly increased, making power consumption a major design concern. High power consumption exacerbates the reliabil...
SystemLevel Power Estimation and Optimization
 Proceedings of ISLPED
, 1998
"... Most work to date on power reduction has focused at the component level, not at the system level. In this paper, we propose a framework for describing the power behavior of systemlevel designs. The model consists of a set of resources, an environmental workload specification, and a power managemen ..."
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Cited by 43 (7 self)
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Most work to date on power reduction has focused at the component level, not at the system level. In this paper, we propose a framework for describing the power behavior of systemlevel designs. The model consists of a set of resources, an environmental workload specification, and a power management policy, which serves as the heart of the system model. We map this model to a simulationbased framework to obtain an estimate of the system's power dissipation. Accompanying this, we propose an algorithm to optimize power management policies. The optimization algorithm can be used in a tight loop with the estimation engine to derive new powermanagement policy algorithms for a given systemlevel description. We tested our approach by applying it to a reallife lowpower portable design, achieving a power estimation accuracy of ~10%, and a 23% reduction in power after policy optimization.
HighLevel Area and Power Estimation for VLSI Circuits
, 1997
"... This paper addresses the problem of computing the area complexity of a multioutput combinational logic circuit, given only its functional description, i.e., Boolean equations, where area complexity is measured in terms of the number of gates required for an optimal multilevel implementation of the ..."
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Cited by 35 (4 self)
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This paper addresses the problem of computing the area complexity of a multioutput combinational logic circuit, given only its functional description, i.e., Boolean equations, where area complexity is measured in terms of the number of gates required for an optimal multilevel implementation of the combinational logic. The proposed area model is based on transforming the given multioutput Boolean function description into an equivalent singleoutput function. The model is empirical, and results demonstrating its feasibility and utility are presented. Also, a methodology for converting the gate count estimates, obtained from the area model, into capacitance estimates is presented. Highlevel power estimates based on the total capacitance estimates and average activity estimates are also presented.
Power Modeling for High Level Power Estimation
 IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, 2000
"... In this paper, we propose a modeling approach that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching statistics. The resulting power macromodel, consisting of a single fourdimensional table, can be used to estimate the power consu ..."
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Cited by 29 (2 self)
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In this paper, we propose a modeling approach that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching statistics. The resulting power macromodel, consisting of a single fourdimensional table, can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a lowlevel (typically gatelevel) description of the circuit, we describe a characterization process by which such a table model can be automatically built. The four dimensions of our tablebased model are the average input signal probability, average input transition density, average spatial correlation coe#cient and average output zerodelay transition density. This approach has been implemented and models have been built for many benchmark circuits. Over a wide range of input signal statistics, we show that this model gives very good accuracy, with an RMS error of about 4% and average error of about 6%. Except for one...
Fullchip verification methods for DSM power distribution systems
 Proceedings of the ACM/IEEE Design Automation Conference
, 1998
"... Power distribution verification is rapidly becoming a necessary step in deep submicron (DSM) design of high performance integrated circuits. With the increased load and reduced tolerances of DSM circuits, more failures are being seen due to poorly designed power distribution systems. This paper desc ..."
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Cited by 23 (0 self)
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Power distribution verification is rapidly becoming a necessary step in deep submicron (DSM) design of high performance integrated circuits. With the increased load and reduced tolerances of DSM circuits, more failures are being seen due to poorly designed power distribution systems. This paper describes an efficient approach for the verification of power distribution at the fullchip transistor level based on a combination of hierarchical static and dynamic techniques. Application of the methodology on practical design examples will be provided. We will also demonstrate the necessity of an analysis at the fullchip transistor level to verify the complex interactions between different design blocks based on static and dynamic effects.
Analytical Model for High Level Power Modeling of Combinational and Sequential Circuits
 In Proc. IEEE Alessandro Volta Workshop on Low Power Design
, 1999
"... In this paper, we propose a modeling approach that captures the dependence of the power dissipation of a (combinational or sequential) logic circuit on its input/output signal switching statistics. The resulting power macromodel, consists of a quadratic or cubic equation in four variables, that can ..."
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Cited by 20 (4 self)
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In this paper, we propose a modeling approach that captures the dependence of the power dissipation of a (combinational or sequential) logic circuit on its input/output signal switching statistics. The resulting power macromodel, consists of a quadratic or cubic equation in four variables, that can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a lowlevel (typically gatelevel) description of the circuit, we describe a characterization process that uses a recursive least squares (RLS) algorithm by which such a equationbased model can be automatically built. The four variables of our model are the average input signal probability, average input switching activity, average input spatial correlation coefficient and average output zerodelay switching activity. This approach has been implemented and models have been built and tested for many combinational and sequential benchmark circuits. 1.
Analytical Estimation of Signal Transition Activity from WordLevel Statistics
 IEEE Trans. on CAD
, 1997
"... Presented in this paper is a novel methodology to determine the average number of transitions in a signal from its wordlevel statistical description. The proposed methodology employs: 1.) highlevel signal statistics, 2.) a statistical signal generation model, and 3.) the signal encoding (or num ..."
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Cited by 19 (2 self)
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Presented in this paper is a novel methodology to determine the average number of transitions in a signal from its wordlevel statistical description. The proposed methodology employs: 1.) highlevel signal statistics, 2.) a statistical signal generation model, and 3.) the signal encoding (or number representation) to estimate the transition activity for that signal. In particular, the signal statistics employed are mean (t), variance (2), and autocorrelation (p). The signal generation models considered are autoregressive movingaverage (ARMA) models. The signal encoding includes unsigned, one's complement, two's complement, and signmagnitude representations.
Analytical Macromodeling for HighLevel Power Estimation
 In Proc. IEEE International Conference on Computer Aided Design
, 1999
"... This paper presents a new macromodeling technique for highlevel power estimation. Our technique is based on a parameterizable analytical model that relies exclusively on statistical information of the circuit's primary inputs. During estimation, the statistics of the required metrics are extra ..."
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Cited by 15 (6 self)
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This paper presents a new macromodeling technique for highlevel power estimation. Our technique is based on a parameterizable analytical model that relies exclusively on statistical information of the circuit's primary inputs. During estimation, the statistics of the required metrics are extracted from the input stream, and a power estimate is obtained by evaluating a model function that has been characterized in advance. Our model yields power estimates within seconds, because it does not rely on the statistics of the circuit's primary outputs and, consequently, does not perform any simulation during estimation. Moreover, it achieves better accuracy than previous macromodeling approaches by taking into account both spatial and temporal correlations in the input stream. In experiments with the ISCAS85 combinational circuits, the average absolute relative error of our power macromodeling technique was at most 1.8%. The worstcase error was at most 12.8%. For a ripplecarry adder fami...
Theeuwen, “Speeding Up Power Estimation of Embedded Software
 in Proc. Int. Symp. Low Power Electronics & Design
, 2000
"... ABSTRACT Power is increasingly becoming a design constraint for embedded systems. A processor is responsible for energy consumption on account of the software component o f t h e e mbedded system. The power estimation of this component is a major concern due to the rising complexities of processors ..."
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Cited by 15 (0 self)
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ABSTRACT Power is increasingly becoming a design constraint for embedded systems. A processor is responsible for energy consumption on account of the software component o f t h e e mbedded system. The power estimation of this component is a major concern due to the rising complexities of processors and the slow estimation tools. This work attempts to estimate the energy dissipation of the PR1900 1 processor based on instruction set model with improved accuracy. The model is integrated in a simulation framework and validated. Over 200 times speedup has been obtained with average 1.4% loss in accuracy over gate level estimation. Analysis of the energy dissipated by the instruction vis a vis the processor architecture has been carried out and a substantial reduction in the measurement e ort to build the processor energy model has been achieved.