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Mapping on multi/many-core systems: survey of current and emerging trends
- In Proceedings of the 50th Annual Design Automation Conference, DAC ’13
, 2013
"... The reliance on multi/many-core systems to satisfy the high performance requirement of complex embedded software ap-plications is increasing. This necessitates the need to real-ize efficient mapping methodologies for such complex com-puting platforms. This paper provides an extensive survey and cate ..."
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The reliance on multi/many-core systems to satisfy the high performance requirement of complex embedded software ap-plications is increasing. This necessitates the need to real-ize efficient mapping methodologies for such complex com-puting platforms. This paper provides an extensive survey and categorization of state-of-the-art mapping methodolo-gies and highlights the emerging trends for multi/many-core systems. The methodologies aim at optimizing system’s re-source usage, performance, power consumption, tempera-ture distribution and reliability for varying application mod-els. The methodologies perform design-time and run-time optimization for static and dynamic workload scenarios, re-spectively. These optimizations are necessary to fulfill the end-user demands. Comparison of the methodologies based on their optimization aim has been provided. The trend followed by the methodologies and open research challenges have also been discussed. Categories and Subject Descriptors C.3 [Special-purpose and application-based systems]: Real-time systems and embedded systems
A Scenario-based Run-time Task Mapping Algorithm for MPSoCs
"... The application workloads in modern MPSoC-based embedded systems are becoming increasingly dynamic. Different applications concurrently execute and contend for resources in such systems which could cause serious changes in the intensity and nature of the workload demands over time. To cope with the ..."
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The application workloads in modern MPSoC-based embedded systems are becoming increasingly dynamic. Different applications concurrently execute and contend for resources in such systems which could cause serious changes in the intensity and nature of the workload demands over time. To cope with the dynamism of application workloads at run time and improve the efficiency of the underlying system architecture, this paper presents a novel scenario-based run-time task mapping algorithm. This algorithm combines a static mapping strategy based on workload scenarios and a dynamic mapping strategy to achieve an overall improvement of system efficiency. We evaluated our algorithm using a homogeneous MPSoC system with three real applications. From the results, we found that our algorithm achieves an 11.3 % performance improvement and a 13.9 % energy saving compared to running the applications without using any run-time mapping algorithm. When comparing our algorithm to three other, well-known run-time mapping algorithms, it is superior to these algorithms in terms of quality of the mappings found while also reducing the overheads compared to most of these algorithms.
An Iterative Multi-Application Mapping Algorithm for Heterogeneous MPSoCs
"... Abstract—Task mapping plays a crucial role in achieving high performance and energy savings in heterogeneous multiprocessor platforms. The problem of optimally mapping tasks onto a set of given heterogeneous processors for maximal throughput/minimal overall energy consumption has been known, in gene ..."
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Abstract—Task mapping plays a crucial role in achieving high performance and energy savings in heterogeneous multiprocessor platforms. The problem of optimally mapping tasks onto a set of given heterogeneous processors for maximal throughput/minimal overall energy consumption has been known, in general, to be NP-complete. This problem is exacerbated when mapping multiple applications onto the target platform. To address this problem, this paper proposes an iterative multi-application mapping algorithm that operates at run time. Based on statically derived optimal (or near optimal) mappings for each separate application, this algorithm will quickly find a near optimal mapping under the objectives of high performance and low energy consumption for the simultaneously running applications on heterogeneous platforms. We have evaluated our algorithm using a heterogeneous MPSoC system with three real applications. Experimental results reveal the effectiveness of our proposed algorithm by comparing derived solutions to the ones obtained from other well-known algorithms. I.
Fast scenario-based design space exploration using feature selection
- in Proc. of the Int. Workshop on Parallel Programming and Run-Time Management Techniques for Manycore Architectures (PARMA’12
, 2012
"... Abstract: This paper presents a novel approach to efficiently perform early system level design space exploration (DSE) of MultiProcessor System-on-Chip (MPSoC) based embedded systems. By modeling dynamic multi-application workloads using application scenarios, optimal designs can be quickly identif ..."
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Abstract: This paper presents a novel approach to efficiently perform early system level design space exploration (DSE) of MultiProcessor System-on-Chip (MPSoC) based embedded systems. By modeling dynamic multi-application workloads using application scenarios, optimal designs can be quickly identified using a combination of a scenario-based DSE and a feature selection algorithm. The feature selection algo-rithm identifies a representative subset of scenarios, which is used to predict the fitness of the MPSoC design instances in the genetic algorithm of the scenario-based DSE. Results show that our scenario-based DSE provides a tradeoff between the speed and accuracy of the early DSE. 1
MODELING AND MAPPING OF OPTIMIZED SCHEDULES FOR EMBEDDED SIGNAL PROCESSING SYSTEMS
, 2013
"... The demand for Digital Signal Processing (DSP) in embedded systems has been increasing rapidly due to the proliferation of multimedia- and communication-intensive devices such as pervasive tablets and smart phones. Efficient implementation of em-bedded DSP systems requires integration of diverse har ..."
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The demand for Digital Signal Processing (DSP) in embedded systems has been increasing rapidly due to the proliferation of multimedia- and communication-intensive devices such as pervasive tablets and smart phones. Efficient implementation of em-bedded DSP systems requires integration of diverse hardware and software components, as well as dynamic workload distribution across heterogeneous computational resources. The former implies increased complexity of application modeling and analysis, but also brings enhanced potential for achieving improved energy consumption, cost or perfor-mance. The latter results from the increased use of dynamic behavior in embedded DSP applications. Furthermore, parallel programming is highly relevant in many embedded DSP areas due to the development and use of Multiprocessor System-On-Chip (MPSoC) technology. The need for efficient cooperation among different devices supporting di-verse parallel embedded computations motivates high-level modeling that expresses dy-namic signal processing behaviors and supports efficient task scheduling and hardware mapping. Starting with dynamic modeling, this thesis develops a systematic design method-
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1 Fitness Prediction Techniques for Scenario-based Design Space Exploration
"... Abstract—Modern embedded systems are becoming increasingly multi-functional. The dynamism in multi-functional embedded systems manifests itself with more dynamic applications and the presence of multiple applications executing on a single embedded system. This dynamism in the application workload mu ..."
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Abstract—Modern embedded systems are becoming increasingly multi-functional. The dynamism in multi-functional embedded systems manifests itself with more dynamic applications and the presence of multiple applications executing on a single embedded system. This dynamism in the application workload must be taken into account during the early system-level design space exploration (DSE) of MultiProcessor System-on-Chip (MPSoC) based embedded systems. Scenario-based DSE utilizes the concept of application scenarios to search for optimal mappings of a multi-application workload onto an MPSoC. The scenario-based DSE uses a multiobjective genetic algorithm (GA) to identifying the mapping that has the best average quality for all the application scenarios in the workload. In order to keep the exploration of the scenariobased DSE efficient, fitness prediction is used to obtain the quality of a mapping. This fitness prediction is performed using a representative subset of application scenarios that is obtained using co-exploration of the scenario subset space. In this paper multiple fitness prediction techniques are presented: stochastic, deterministic and a hybrid combination. Results show that, for our test cases, accurate fitness prediction is already provided for subsets containing only 1 − 4 % of the application scenarios. Larger subsets will obtain a similar accuracy, but the DSE will require more time to identify promising mappings that meet the requirements of multi-functional embedded systems.
Using Chip Multithreading to Speed Up Scenario-Based Design Space Exploration ∗
"... To cope with the complex embedded system design, early design space exploration (DSE) is used to make design decisions early in the design phase. For early DSE it is crucial that the running time of the ex-ploration is as small as possible. In this paper, we describe both the porting of our scenario ..."
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To cope with the complex embedded system design, early design space exploration (DSE) is used to make design decisions early in the design phase. For early DSE it is crucial that the running time of the ex-ploration is as small as possible. In this paper, we describe both the porting of our scenario-based DSE to the SPARC T3-4 server and the analysis of its per-formance behavior. 1
Towards an ESL Design Framework for Adaptive and Fault-tolerant MPSoCs: MADNESS or not?
"... Abstract—The MADNESS project aims at the definition of innovative system-level design methodologies for embedded MP-SoCs, extending the classic concept of design space exploration in multi-application domains to cope with high heterogeneity, technology scaling and system reliability. The main goal o ..."
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Abstract—The MADNESS project aims at the definition of innovative system-level design methodologies for embedded MP-SoCs, extending the classic concept of design space exploration in multi-application domains to cope with high heterogeneity, technology scaling and system reliability. The main goal of the project is to provide a framework able to guide designers and researchers to the optimal composition of embedded MPSoC architectures, according to the requirements and the features of a given target application field. The proposed approach will tackle the new challenges, related to both archi-tecture and design methodologies, arising with the technology scaling, the system reliability and the ever-growing computational needs of modern applications. The methodologies proposed with this project act at different levels of the design flow, enhancing the state-of-the art with novel features in system-level synthesis, architectural evaluation and prototyping. Support for fault resilience and efficient adaptive runtime management is introduced at hardware and middleware level, and considered by the system-level synthesis as one of the optimization factors to be taken into account. This paper presents the first stable results obtained in the MADNESS project, already demonstrating the effectiveness of the proposed methods. I.
