www.elsevier.com/locate/jpdc Exploiting NIC architectural support for enhancing IP-based protocols on high-performance networks

This paper presents the MPC parallel computer and its MPI implementation performed at the Laboratoire LIP6 of Univ. Pierre and Marie Curie, Paris. MPC is a low cost and high performance parallel computer using standard PC main-boards as processing nodes connected through the specific FastHSL board to a high speed communication network using HSL 1 Gbits/s serial links, IEEE 1355 compliant. Two Asics are presented : RCUBE which is the HSL network router, and PCI-DDC the network controller implementing the Direct Deposit State Less receiver protocol.

One of the key concerns for practitioners and academicians is that there are almost no platforms based on analytical models for testing the impact of various architectural and design modifications for intelligent Network Interface Cards (NICs). Simulations are typically time-consuming, especially for experimenting different scenarios and what-if analysis. In this research, we study the performance of a NIC called Myrinet developed by Myricom. We develop an open queueing network model to predict its performance. We compare the analytical results with the simulations. The reason there are very few analytical models is because of the enormous complexity posed by the performance-analysis problem. In particular, the problem is a combination of: (a) multi-class queueing network with class switching, (b) polling system with limited service discipline, and (c) finite-capacity queues with blocking. The above three issues have been treated only in isolation in the literature. However the problem becomes much harder when all three issues are simultaneously present. One of the key contributions of this paper is an analytical approximation of this complex system. From an analytical modeling standpoint, we observe that making simplifying assumptions to analyze nodes that are not bottlenecks does not impact performance greatly. The main findings of this research are the bottlenecks of the queueing network, utilizations of the various nodes and performance measures such as the expected delay. The model as well as findings can be used to test the performance impact of various enhancements to the operation of NICs.