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Gate Sizing for Constrained delay/power/area optimization
 in IEEE Transcation on VLSI Design
, 1997
"... Abstract—Gate sizing has a significant impact on the delay, power dissipation, and area of the final circuit. It consists of choosing for each node of a mapped circuit a gate implementation in the library so that a cost function is optimized under some constraints. For instance, one wants to mini ..."
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Cited by 40 (1 self)
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Abstract—Gate sizing has a significant impact on the delay, power dissipation, and area of the final circuit. It consists of choosing for each node of a mapped circuit a gate implementation in the library so that a cost function is optimized under some constraints. For instance, one wants to minimize the power consumption and/or the area of a circuit under some userdefined delay constraints, or to obtain the fastest circuit within a given power budget. Although this technologydependent optimization has been investigated for years, the proposed approaches sometimes rely on assumptions, cost models, or algorithms that make them unrealistic or impossible to apply on reallife large circuits. We discusse here a gate sizing algorithm (GS), and show how it is used to achieve constrained optimization. It can be applied on large circuits within a reasonable CPU time, e.g., minimizing the power of a 10000 nodes circuit under some delay constraint in 2 hours. Keywords—Gate sizing, discrete constrained optimization, delay/power/area tradeoff I.
Scheduling Techniques for Variable Voltage Low Power Designs
 ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
, 1997
"... This paper presents an integer linear programming (ILP) model and a heuristic for the variable voltage scheduling problem. We present the variable voltage scheduling techniques that consider in turn timing constraints alone, resource constraints alone, and timing and resource constraints together fo ..."
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Cited by 39 (0 self)
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This paper presents an integer linear programming (ILP) model and a heuristic for the variable voltage scheduling problem. We present the variable voltage scheduling techniques that consider in turn timing constraints alone, resource constraints alone, and timing and resource constraints together for design space exploration. Experimental results show that our heuristic produces results competitive with those of the ILP method in a fraction of the runtime. The results also show that a wide range of design alternatives can be generated using our design space exploration method. Using different cost/delay combinations, power consumption in a single design can differ by as much as a factor of 6 when using mixed 3.3V and 5V supply voltages
Techniques for the Power Estimation of Sequential Logic Circuits Under UserSpecified Input Sequences and Programs
 IEEE Transactions on VLSI Systems
, 1994
"... We describe an approach to estimate the average power dissipation in sequential logic circuits under userspecified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the estimation of the power dissipated when the controller or proc ..."
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Cited by 38 (9 self)
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We describe an approach to estimate the average power dissipation in sequential logic circuits under userspecified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the estimation of the power dissipated when the controller or processor is running specific application programs. Current approaches to sequential circuit power estimation are limited by the fact that the input sequences to the sequential circuit are assumed to be uncorrelated. In reality, the inputs come from other sequential circuits, or are application programs. In this paper we show how userspecified sequences and programs can be modeled using a finite state machine, termed an inputmodeling finite state machines or IMFSM. Power estimation can be carried out using existing sequential circuit power estimation methods on a cascade circuit consisting of the IMFSM and the original sequential circuit. I. INTRODUCTION Average power dissipation estimation is...
New Algorithms for Gate Sizing: A Comparative Study
 IN DAC
, 1996
"... Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. It has a significant impact on the delay, power dissipation, and area of the final circuit. This paper compares five gate sizing alg ..."
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Cited by 37 (1 self)
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Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. It has a significant impact on the delay, power dissipation, and area of the final circuit. This paper compares five gate sizing algorithms targeting discrete, nonlinear, nonunimodal, constrained optimization. The goal is to overcome the nonlinearity and nonunimodality of the delay and the power to achieve good quality results within a reasonable CPU time, e.g., handling a 10000 node network in 2 hours. We compare the five algorithms on constraint free delay optimization and delay constrained power optimization, and show that one method is superior to the others.
A detailed power model for fieldprogrammable gate arrays
 Design Automation of Electronic Systems (TODAES
, 2005
"... Power has become a critical issue for FPGA vendors. Understanding the power dissipation within FPGAs is the first step to develop powerefficient architectures and CAD tools for FPGAs. This paper describes a detailed and flexible power model which has been integrated in the widelyused Versatile Pla ..."
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Cited by 33 (6 self)
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Power has become a critical issue for FPGA vendors. Understanding the power dissipation within FPGAs is the first step to develop powerefficient architectures and CAD tools for FPGAs. This paper describes a detailed and flexible power model which has been integrated in the widelyused Versatile Place and Route (VPR) CAD tool. This power model estimates the dynamic, shortcircuit, and leakage power consumed by FPGAs. It is the first flexible power model developed to evaluate architectural tradeoffs and the efficiency of poweraware CAD tools for a variety of FPGA architectures, and is freely available for noncommercial use. The model is flexible, in that it can estimate the power for a wide variety of FPGA architectures, and it is fast, in that it does not require extensive simulation, meaning it can be used to explore a large architectural space. We show how the model can be used to investigate the impact of various architectural parameters on the energy consumed by the FPGA, focusing on the segment length, switch block topology, lookuptable size, and cluster size.
FunctionLevel Power Estimation Methodology for Microprocessors
, 2000
"... We have developed a functionlevel power estimation methodology for predicting the power dissipation of embedded software. For a given microprocessor core, we empirically build the "power data bank", which stores the power information of the builtin library functions and basic instruction ..."
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Cited by 33 (0 self)
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We have developed a functionlevel power estimation methodology for predicting the power dissipation of embedded software. For a given microprocessor core, we empirically build the "power data bank", which stores the power information of the builtin library functions and basic instructions. To estimate the average power of an embedded software on this core, we first get the execution information of the target software from program profiling/tracing tools. Then we evaluate the total energy consumption and execution time based on the "power data bank", and take their ratio as the average power. High efficiency is achieved because no power simulator is used once the "power data bank" is built. We apply this method to a commercial microprocessor core and get power estimates with an average error of 3%. With this method, microprocessor vendors can provide users the "power data bank" without releasing details of the core to help users get early power estimates and eventually guide power optimization.
Toward Achieving Energy Efficiency in Presence of Deep Submicron Noise
 IEEE TRANSACTIONS ON VLSI SYSTEMS
, 2000
"... Presented in this paper are 1) informationtheoretic lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy efficiency in the presence of noise. In particular, lower bounds on a) circuit speed and supply voltage ; b) transition ..."
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Cited by 31 (2 self)
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Presented in this paper are 1) informationtheoretic lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy efficiency in the presence of noise. In particular, lower bounds on a) circuit speed and supply voltage ; b) transition activity in presence of noise; c) dynamic energy dissipation; and d) total (dynamic and static) energy dissipation are derived. A surprising result is that in a scenario where dynamic component of power dissipation dominates, the supply voltage for minimum energy operation ( ) is greater than the minimum supply voltage ( min ) for reliable operation. We then propose noise tolerance via coding to approach the lower bounds on energy dissipation. We show that the lower bounds on energy for an offchip I/O signaling example are a factor of 24 below present day systems. A very simple Hamming code can reduce the energy consumption by a factor of 3 , while ReedMuller (RM) codes give a 4 reduction in energy dissipation.
Power Estimation in Sequential Circuits
, 1995
"... A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences to the circuit, statistics on the latch outputs are collected, by simulation, that allow efficient power estimation for the whole ..."
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Cited by 30 (6 self)
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A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences to the circuit, statistics on the latch outputs are collected, by simulation, that allow efficient power estimation for the whole design. An important advantage of this approach is that the desired accuracy can be specified upfront by the user; the algorithm iterates until the specified accuracy is achieved. This has been implemented and tested on a number of sequential circuits and found to be much faster than existing techniques. We can complete the analysis of a circuit with 1,452 flipflops and 19,253 gates in about 4.6 hours (the largest test case reported previously has 223 flipflops). I. INTRODUCTION The dramatic decrease in feature size and the corresponding increase in the number of devices on a chip, combined with the growing demand for portable communication and computing systems, have made power consump...
A mathematical basis for powerreduction in digital VLSI systems,”
 IEEE Trans. Circuits Syst. II,
, 1997
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Power Modeling for High Level Power Estimation
 IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, 2000
"... In this paper, we propose a modeling approach that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching statistics. The resulting power macromodel, consisting of a single fourdimensional table, can be used to estimate the power consu ..."
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Cited by 29 (2 self)
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In this paper, we propose a modeling approach that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching statistics. The resulting power macromodel, consisting of a single fourdimensional table, can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a lowlevel (typically gatelevel) description of the circuit, we describe a characterization process by which such a table model can be automatically built. The four dimensions of our tablebased model are the average input signal probability, average input transition density, average spatial correlation coe#cient and average output zerodelay transition density. This approach has been implemented and models have been built for many benchmark circuits. Over a wide range of input signal statistics, we show that this model gives very good accuracy, with an RMS error of about 4% and average error of about 6%. Except for one...