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270
A Predictive System Shutdown Method for Energy Saving of EventDriven Computation
, 1997
"... This paper presents a systemlevel power management technique for energy saving of eventdriven applications. We present a new predictive systemshutdown method to exploit sleep mode operations for energy saving. We use an exponentialaverage approach to predict the upcoming idle period. We introduc ..."
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Cited by 208 (0 self)
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This paper presents a systemlevel power management technique for energy saving of eventdriven applications. We present a new predictive systemshutdown method to exploit sleep mode operations for energy saving. We use an exponentialaverage approach to predict the upcoming idle period. We introduce two mechanisms, predictionmiss correction and prewakeup, to improve the hit ratio and to reduce the delay overhead. Experiments on four different eventdriven applications show that our proposed method achieves high hit ratios in a wide range of delay overheads, which results in a high degree of energy saving with low delay penalties.
Synthesis Techniques for Lowpower Hard Realtime
 Systems on Variable Voltage Processors,” in IEEE Realtime Systems Symposium,
, 1998
"... ..."
HighLevel Power Modeling, Estimation, and Optimization
 IEEE Trans. On Computer Aided Design
, 1998
"... Abstract—Silicon area, performance, and testability have been, so far, the major design constraints to be met during the development of digital verylargescaleintegration (VLSI) systems. In recent years, however, things have changed; increasingly, power has been given weight comparable to the othe ..."
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Cited by 106 (12 self)
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Abstract—Silicon area, performance, and testability have been, so far, the major design constraints to be met during the development of digital verylargescaleintegration (VLSI) systems. In recent years, however, things have changed; increasingly, power has been given weight comparable to the other design parameters. This is primarily due to the remarkable success of personal computing devices and wireless communication systems, which demand highspeed computations with low power consumption. In addition, there exists a strong pressure for manufacturers of highend products to keep power under control, due to the increased costs of packaging and cooling this type of devices. Last, the need of ensuring high circuit reliability has turned out to be more stringent. The availability of tools for the automatic design of lowpower VLSI systems has thus become necessary. More specifically, following a natural trend, the interests of the researchers have lately shifted to the investigation of power modeling, estimation, synthesis, and optimization techniques that account for power dissipation during the early stages of the design flow. This paper surveys representative contributions to this area that have appeared in the recent literature. Index Terms — Behavioral and logic synthesis, low power design, power management. I.
Towards a HighLevel Power Estimation Capability
 IEEE trans. on CAD
, 1996
"... We will present a power estimation technique for digital integrated circuits that operates at the register transfer level (RTL). Such a highlevel power estimation capability is required in order to provide early warning of any power problems, before the circuitlevel design has been specified. With ..."
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Cited by 96 (10 self)
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We will present a power estimation technique for digital integrated circuits that operates at the register transfer level (RTL). Such a highlevel power estimation capability is required in order to provide early warning of any power problems, before the circuitlevel design has been specified. With such early warning, the designer can explore design tradeoffs at a higher level of abstraction than previously possible, reducing design time and cost. Our estimator is based on the use of entropy as a measure of the average activity to be expected in the final implementation of a circuit, given only its Boolean functional description. This technique has been implemented and tested on a variety of circuits. The empirical results to be presented are very promising and demonstrate the feasibility and utility of this approach. y This work was supported in part by Intel Corp., Santa Clara, CA. Submitted to the IEEE Transactions on CAD, 1995. 1. Introduction The high device count and operati...
An InformationTheoretic Model for Adaptive SideChannel Attacks
 CCS'07
, 2007
"... We present a model of adaptive sidechannel attacks which we combine with informationtheoretic metrics to quantify the information revealed to an attacker. This allows us to express an attacker’s remaining uncertainty about a secret as a function of the number of sidechannel measurements made. We ..."
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Cited by 85 (8 self)
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We present a model of adaptive sidechannel attacks which we combine with informationtheoretic metrics to quantify the information revealed to an attacker. This allows us to express an attacker’s remaining uncertainty about a secret as a function of the number of sidechannel measurements made. We present algorithms and approximation techniques for computing this measure. We also give examples of how they can be used to analyze the resistance of hardware implementations of cryptographic functions to both timing and power attacks.
A survey of optimization techniques targeting low power circuits
 in Proc. Design Automation Conf
, 1995
"... Abstract—We survey stateoftheart optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are considered. Keywords—low power, optimization, synthesis I. ..."
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Cited by 77 (0 self)
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Abstract—We survey stateoftheart optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are considered. Keywords—low power, optimization, synthesis I.
Power Macromodeling for High Level Power Estimation
, 1997
"... A modeling approach is presented that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching activity. The resulting power macromodel, consisting of a single three dimensional table, can be used to estimate the power consumed in the cir ..."
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Cited by 73 (9 self)
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A modeling approach is presented that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching activity. The resulting power macromodel, consisting of a single three dimensional table, can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a lowlevel (typically gatelevel) description of the circuit, we describe a characterization process by which such a table model can be automatically built. In contrast to other proposed techniques, this can be done for any given logic circuit without any user intervention, and applies to all possible input/output signal statistics; it does not require one to construct specialized analytical equations for the power dissipation. The three dimensions of our tablebased model are the average input signal probability, average input transition density, and average output zerodelay transition density. This approach has been implemented and models...
Information Theoretic Measures for Power Analysis
, 1996
"... This paper considers the problem of estimating the power consumption at logic and register transfer levels of design from an information theoretical point of view. In particular, it is demonstrated that the average switching activity in the circuit can be calculated using either entropy or informati ..."
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Cited by 48 (9 self)
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This paper considers the problem of estimating the power consumption at logic and register transfer levels of design from an information theoretical point of view. In particular, it is demonstrated that the average switching activity in the circuit can be calculated using either entropy or informational energy averages. For control circuits and random logic, the output entropy (informational energy) per bit is calculated as a function of the input entropy (informational energy) per bit and an implementation dependent information scaling factor. For datapath circuits, the output entropy (informational energy) is calculated from the input entropy (informational energy) using a compositional technique which has linear complexity in terms of the circuit size. Finally, from these input and output value, the entropy (informational energy) per circuit line is calculated and used as an estimate for the average switching activity. The proposed switching activity estimation technique does not r...
A matrix synthesis approach to thermal placement
 Proc. TCAD
, 1998
"... Abstract — In this paper, we consider the thermal placement problem for gate arrays. We introduce a new combinatorial optimization problem, matrix synthesis problem (MSP), to model the thermal placement problem. Given a list of mn nonnegative real numbers and an integer t, MSP constructs a m 2 n mat ..."
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Cited by 45 (0 self)
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Abstract — In this paper, we consider the thermal placement problem for gate arrays. We introduce a new combinatorial optimization problem, matrix synthesis problem (MSP), to model the thermal placement problem. Given a list of mn nonnegative real numbers and an integer t, MSP constructs a m 2 n matrix out of the given numbers such that the maximum sum among all t 2 t submatrices is minimized. We show that MSP is NPcomplete and present several provably good approximation algorithms for the problem. We also demonstrate that our thermal placement strategy is flexible enough to allow simultaneous consideration of other objectives such as wiring. Index Terms—Approximation algorithm, thermal placement. I.
SystemLevel PowerAware Design Techniques in RealTime Systems
 Proceedings of the IEEE
, 2003
"... Power and energy consumption has recently become an important issue and consequently, poweraware techniques are being devised at all levels of system design; from the circuit and device level, to the architectural, compiler, operating system and networking layers. In this survey we concentrate on p ..."
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Cited by 41 (2 self)
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Power and energy consumption has recently become an important issue and consequently, poweraware techniques are being devised at all levels of system design; from the circuit and device level, to the architectural, compiler, operating system and networking layers. In this survey we concentrate on poweraware design techniques for realtime systems. While the main focus is on hard realtime, soft realtime systems are considered as well. We start with the motivation for focusing on these systems and provide a brief discussion on power and energy objectives. We then follow with a survey of current research on a layer by layer basis. We conclude with illustrative examples and open research challenges. This work provides an overview of poweraware techniques for the realtime system engineer as well as an uptodate reference list for the researcher.