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Sorting and Searching in the Presence of Memory Faults (without Redundancy)
 Proc. 36th ACM Symposium on Theory of Computing (STOC’04
, 2004
"... We investigate the design of algorithms resilient to memory faults, i.e., algorithms that, despite the corruption of some memory values during their execution, are able to produce a correct output on the set of uncorrupted values. In this framework, we consider two fundamental problems: sorting and ..."
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Cited by 21 (4 self)
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We investigate the design of algorithms resilient to memory faults, i.e., algorithms that, despite the corruption of some memory values during their execution, are able to produce a correct output on the set of uncorrupted values. In this framework, we consider two fundamental problems: sorting and searching. In particular, we prove that any O(n log n) comparisonbased sorting algorithm can tolerate at most O((n log n) ) memory faults. Furthermore, we present one comparisonbased sorting algorithm with optimal space and running time that is resilient to O((n log n) ) faults. We also prove polylogarithmic lower and upper bounds on faulttolerant searching.
SharedMemory Simulations on a FaultyMemory DMM
, 1996
"... this paper are synchronous, and the time performance is our major efficiency criterion. We consider a DMM with faulty memory words, otherwise everything is assumed to be operational. In particular the communication between the processors and the MUs is reliable, and a processor may always attempt to ..."
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Cited by 10 (1 self)
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this paper are synchronous, and the time performance is our major efficiency criterion. We consider a DMM with faulty memory words, otherwise everything is assumed to be operational. In particular the communication between the processors and the MUs is reliable, and a processor may always attempt to obtain an access to any MU, and, having been granted it, may access any memory word in it, even if all of them are faulty. The only restriction on the distribution of faults among memory words is that their total number is bounded from above by a fraction of the total number of memory words in all the MUs. In particular, some MUs may contain only operational cells, some only faulty cells, and some mixed cells. This report presents fast simulations of the PRAM on a DMM with faulty memory.
Deterministic Computations on a PRAM with Static Faults
"... We develop a deterministic simulation of fully operational Parallel Random Access Machine (PRAM) on a PRAM with some faulty processors and memory cells. The faults considered are static, i.e., once the machine starts to operate, the operational/faulty status of PRAM components does not change. The s ..."
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Cited by 6 (0 self)
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We develop a deterministic simulation of fully operational Parallel Random Access Machine (PRAM) on a PRAM with some faulty processors and memory cells. The faults considered are static, i.e., once the machine starts to operate, the operational/
2000
faulty status of PRAM components does not change. The simulating machine can tolerate a constant fraction of faults among processors and memory cells. The simulating PRAM has n processors and m memory cells, and simulates a PRAM with n processors and m) memory cells. The simulation is in three phases: (1) preprocessing, followed by (2) retrieving the input by the processors active in the simulation, followed by (3) the proper part of the simulation performed in a stepbystep fashion. Preprocessing is performed in time O(( m n + log n) log n). The input is retrieved in time O(log 2 n). The slowdown of the proper part of the simulation is O(log m).
We develop a deterministic simulation of fully operational Parallel Random Access Machine (PRAM) on a PRAM with some faulty processors and memory cells. The faults considered are static, i.e., once the machine starts to operate, the operational/faulty status of PRAM components does not change. The simulating machine can tolerate a constant fraction of faults among processors and memory cells. The simulating PRAM has n processors and m memory cells, and simulates a PRAM with n processors and m) memory cells. The simulation is in three phases: (1) preprocessing, followed by (2) retrieving the input by the processors active in the simulation, followed by (3) the proper part of the simulation performed in a stepbystep fashion. Preprocessing is performed in time O(( m n + log n) log n). The input is retrieved in time O(log 2 n). The slowdown of the proper part of the simulation is O(log m).