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88
Power Minimization in IC Design: Principles and Applications
 ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
, 1996
"... Low power has emerged as a principal theme in today’s electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an indepth survey of CAD methodologies and techniques for designing low powe ..."
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Cited by 197 (28 self)
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Low power has emerged as a principal theme in today’s electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an indepth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logic and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.
Automatic synthesis of burstmode asynchronous controllers
, 1995
"... Asynchronous design has enjoyed a revival of interest recently, as designers seek to eliminate penalties of traditional synchronous design. In principle, asynchronous methods promise to avoid overhead due to clock skew, worstcase design assumptions and resynchronization of asynchronous external inp ..."
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Cited by 75 (10 self)
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Asynchronous design has enjoyed a revival of interest recently, as designers seek to eliminate penalties of traditional synchronous design. In principle, asynchronous methods promise to avoid overhead due to clock skew, worstcase design assumptions and resynchronization of asynchronous external inputs. In practice, however, many asynchronous design methods suffer from a number of problems: unsound algorithms (implementations may have hazards), harsh restrictions on the range of designs that can be handled (singleinput changes only), incompatibility with existing design styles and inefficiency in the resulting circuits. This thesis presents a new locallyclocked design method for the synthesis of asynchronous controllers. The method has been automated, is proven correct and produces highperformance implementations which are hazardfree at the gatelevel. Implementations allow multipleinput changes and handle a relatively unconstrained class of behaviors (called "burstmode" specifications). The method produces statemachine implementations with a minimal or nearminimal number of states. Implementations can be easily built in such common VLSI design styles as gatearray, standard cell and fullcustom. Realizations typically have the latency of
NanowireBased Sublithographic Programmable Logic Arrays
, 2004
"... How can Programmable Logic Arrays (PLAs) be built without relying on lithography to pattern their smallest features? In this paper, we detail designs which exploit emerging, bottomup material synthesis techniques to build PLAs using molecularscale nanowires. Our new designs accommodate technologie ..."
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Cited by 46 (6 self)
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How can Programmable Logic Arrays (PLAs) be built without relying on lithography to pattern their smallest features? In this paper, we detail designs which exploit emerging, bottomup material synthesis techniques to build PLAs using molecularscale nanowires. Our new designs accommodate technologies where the only postfabrication programmable element is a nonrestoring diode. We introduce stochastic techniques which allow us to restore the diode logic at the nanoscale so that it can be cascaded and interconnected for general logic evaluation. Under conservative assumptions using 10nm nanowires and 90nm lithographic support, we project yielded logic density around 500,000nm 2 /or term for a 60 orterm array; a complete 60term, twolevel PLA is roughly the same size as a single 4LUT logic block in 22nm lithography. Each or term is comparable in area to a 4transistor hardwired gate at 22nm. Mapping sample datapaths and conventional programmable logic benchmarks, we estimate that each 60orterm PLA plane will provide equivalent logic to 5–10 4input LUTs.
Low Power State Assignment Targeting Two and Multilevel Logic Implementations
, 1994
"... The problem of minimizing power consumption during the state encoding of a finite state machine is considered. A new power cost model for state encoding is proposed and encoding techniques that minimize this power cost for twoand multilevel logic implementations are described. These techniques are ..."
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Cited by 25 (7 self)
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The problem of minimizing power consumption during the state encoding of a finite state machine is considered. A new power cost model for state encoding is proposed and encoding techniques that minimize this power cost for twoand multilevel logic implementations are described. These techniques are compared with those which minimize area or the switching activity at the present state bits. Experimental results show significant improvements. 1 Introduction In this work, we address the problem of minimizing the power consumption in sequential machines. Since the power consumption in a finite state machine (FSM) is strongly influenced by state encoding of the machine, we set as our goal the development of encoding algorithms that lead to low power implementations after two or multilevel logic optimization. State assignment algorithms that minimize the area of the circuit after logic optimization have been extensively researched. This problem is NPhard and various methods have been pro...
Optimum and Suboptimum Algorithms for Input Encoding and its Relationship to Logic Minimization
 IEEE Trans. on CAD
, 1991
"... A new theoretical formulation of the input encoding problem is presented, based on the concept of compatibility of dichotomies. The input encoding problem is shown to be equivalent to a twolevel logic minimization. Three possible techniques to solve the encoding problem are discussed, based on: 1) ..."
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Cited by 22 (5 self)
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A new theoretical formulation of the input encoding problem is presented, based on the concept of compatibility of dichotomies. The input encoding problem is shown to be equivalent to a twolevel logic minimization. Three possible techniques to solve the encoding problem are discussed, based on: 1) techniques borrowed from classical logic minimization (generation of prime dichotomies and solving the covering problem), 2) graph coloring applied to the graph of incompatibility of dichotomies, and 3) extraction of essential prime dichotomies followed by graph coloring. The extraction of essential prime dichotomies serves the same purpose as the extraction of essential prime implicants in logic minimization, in the sense that it reduces the size of the covering/graph coloring problem. The conditions of optimality of the solutions to the input encoding problem are discussed. For nearoptimum results a powerful heuristic, based on iterative improvement technique, has been developed and imple...
Resolution, Optimization, and Encoding of Pointer Variables for the Behavioral Synthesis from C
, 2001
"... As designers may model mixed hardwaresoftware systems using a subset of or ++, we present SpC, a solution to synthesize and optimize hardware models with pointers. In hardware, a pointer is not only the address of data in memory, but it may also reference data mapped to registers, ports, or wires. ..."
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Cited by 12 (2 self)
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As designers may model mixed hardwaresoftware systems using a subset of or ++, we present SpC, a solution to synthesize and optimize hardware models with pointers. In hardware, a pointer is not only the address of data in memory, but it may also reference data mapped to registers, ports, or wires. Pointer analysis is used to find the set of locations each pointer may reference in a program at compile time. In this paper, we address the problem of synthesizing and optimizing pointers to multiple variables or array elements. The value of the pointers are encoded and branching statements are used to dynamically access data referenced by pointers. A heuristic is used to efficiently encode the values of the pointers. Compiler techniques are also used to reduce storage before loads and stores. An implementation using the SUIF framework (Wilson et al., 1994; SUIF Compiler Framework) is presented, followed by some case studies and experimental results.
Designing Genetic Algorithms for the State Assignment Problem
 IEEE Transactions on Systems, Man, and Cybernetics
, 1995
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Compact SOP Representations for MultipleOutput Functions  An Encoding Method using MultipleValued Logic 
, 2001
"... This paper shows a method to represent a multipleoutput function: Encoded characteristic function for nonzero outputs (ECFN). The ECFN uses (n + u) binary variables to represent an ninput moutput function, where u = dlog 2 me. The size of the sumofproducts expressions (SOPs) depends on the enc ..."
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Cited by 9 (8 self)
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This paper shows a method to represent a multipleoutput function: Encoded characteristic function for nonzero outputs (ECFN). The ECFN uses (n + u) binary variables to represent an ninput moutput function, where u = dlog 2 me. The size of the sumofproducts expressions (SOPs) depends on the encoding method of the outputs. For some class of functions, the optimal encoding produces SOPs with O(n) products, while the worst encoding produces SOPs with O(2 n ) products. We formulate encoding problem and show a heuristic optimization method. Experimental results using standard benchmark functions show the usefulness of the method. Index term: Multipleoutput function, encoding problem, multiplevalued logic, TDM, SOP, characteristic function. 1.