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A Survey of Power Estimation Techniques in VLSI Circuits
 IEEE Transactions on VLSI Systems
, 1994
"... With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a c ..."
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Cited by 270 (16 self)
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With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. In this paper, we present a review/tutorial of the power estimation techniques that have recently been proposed. Invited, IEEE Trans. on VLSI, Dec. 1994. 1. Introduction The continuing decrease in feature size and the corresponding increase in chip density and operating frequency have made power consumption a major concern in VLSI design [1, 2]. Modern microprocessors are indeed hot: the PowerPC chip from Motorola consumes 8.5 Watts, the Pentium chip from Intel consumes 16 Watts, and DEC's alpha chip consumes 30 Watts. Excessive power dissipation in integrated circuits not only discourages their use in a portable environment, but also causes overheating, which degr...
Probabilistic Symbolic Model Checking with PRISM: A Hybrid Approach
 International Journal on Software Tools for Technology Transfer (STTT
, 2002
"... In this paper we introduce PRISM, a probabilistic model checker, and describe the ecient symbolic techniques we have developed during its implementation. PRISM is a tool for analysing probabilistic systems. It supports three models: discretetime Markov chains, continuoustime Markov chains and ..."
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Cited by 207 (32 self)
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In this paper we introduce PRISM, a probabilistic model checker, and describe the ecient symbolic techniques we have developed during its implementation. PRISM is a tool for analysing probabilistic systems. It supports three models: discretetime Markov chains, continuoustime Markov chains and Markov decision processes. Analysis is performed through model checking speci cations in the probabilistic temporal logics PCTL and CSL. Motivated by the success of model checkers such as SMV, which use BDDs (binary decision diagrams), we have developed an implementation of PCTL and CSL model checking based on MTBDDs (multiterminal BDDs) and BDDs. Existing work in this direction has been hindered by the generally poor performance of MTBDDbased numerical computation, which is often substantially slower than explicit methods using sparse matrices. We present a novel hybrid technique which combines aspects of symbolic and explicit approaches to overcome these performance problems. For typical examples, we achieve orders of magnitude speedup compared to MTBDDs and are able to almost match the speed of sparse matrices whilst maintaining considerable space savings.
HighLevel Power Modeling, Estimation, and Optimization
 IEEE Trans. On Computer Aided Design
, 1998
"... Abstract—Silicon area, performance, and testability have been, so far, the major design constraints to be met during the development of digital verylargescaleintegration (VLSI) systems. In recent years, however, things have changed; increasingly, power has been given weight comparable to the othe ..."
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Cited by 106 (12 self)
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Abstract—Silicon area, performance, and testability have been, so far, the major design constraints to be met during the development of digital verylargescaleintegration (VLSI) systems. In recent years, however, things have changed; increasingly, power has been given weight comparable to the other design parameters. This is primarily due to the remarkable success of personal computing devices and wireless communication systems, which demand highspeed computations with low power consumption. In addition, there exists a strong pressure for manufacturers of highend products to keep power under control, due to the increased costs of packaging and cooling this type of devices. Last, the need of ensuring high circuit reliability has turned out to be more stringent. The availability of tools for the automatic design of lowpower VLSI systems has thus become necessary. More specifically, following a natural trend, the interests of the researchers have lately shifted to the investigation of power modeling, estimation, synthesis, and optimization techniques that account for power dissipation during the early stages of the design flow. This paper surveys representative contributions to this area that have appeared in the recent literature. Index Terms — Behavioral and logic synthesis, low power design, power management. I.
Implementation of Symbolic Model Checking for Probabilistic Systems
, 2002
"... In this thesis, we present ecient implementation techniques for probabilistic model checking, a method which can be used to analyse probabilistic systems such as randomised distributed algorithms, faulttolerant processes and communication networks. A probabilistic model checker inputs a probabilist ..."
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Cited by 72 (21 self)
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In this thesis, we present ecient implementation techniques for probabilistic model checking, a method which can be used to analyse probabilistic systems such as randomised distributed algorithms, faulttolerant processes and communication networks. A probabilistic model checker inputs a probabilistic model and a speci cation, such as \the message will be delivered with probability 1", \the probability of shutdown occurring is at most 0.02" or \the probability of a leader being elected within 5 rounds is at least 0.98", and can automatically verify if the speci cation is true in the model.
Multi Terminal Binary Decision Diagrams to Represent and Analyse Continuous Time Markov Chains
, 1999
"... Binary Decision Diagrams (BDDs) have gained high attention in the context of design and verification of digital circuits. They have successfully been employed to encode very large state spaces in an efficient, symbolic way. Multi terminal BDDs (MTBDDs) are generalisations of BDDs from Boolean va ..."
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Cited by 60 (12 self)
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Binary Decision Diagrams (BDDs) have gained high attention in the context of design and verification of digital circuits. They have successfully been employed to encode very large state spaces in an efficient, symbolic way. Multi terminal BDDs (MTBDDs) are generalisations of BDDs from Boolean values to values of any finite domain. In this paper, we investigate the applicability of MTBDDs to the symbolic representation of continuous time Markov chains, derived from highlevel formalisms, such as queueing networks or process algebras. Based on this data structure, we discuss iterative solution algorithms to compute the steadystate probability vector that work in a completely symbolic way. We highlight a number of lessons learned, using a set of small examples.
Symbolic Model Checking of Concurrent Probabilistic Systems Using MTBDDs
, 2000
"... Symbolic model checking for purely probabilistic processes using MTBDDs [12] was introduced in [4] and further developed in [20, 3]. In this paper we consider models for concurrent probabilistic systems similar to those of [28, 7, 5] and the concurrent Markov chains of [35, 13], which extend the ..."
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Cited by 38 (16 self)
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Symbolic model checking for purely probabilistic processes using MTBDDs [12] was introduced in [4] and further developed in [20, 3]. In this paper we consider models for concurrent probabilistic systems similar to those of [28, 7, 5] and the concurrent Markov chains of [35, 13], which extend the purely probabilistic processes through the addition of nondeterministic choice. As a specification formalism we use the probabilistic branchingtime temporal logic PBTL of [5, 7], which allows us to express properties such as "under any scheduling of nondeterministic choices, the probability of OE holding until / is true is at least 0.78". In [5, 7] it is shown that the verification of "until" properties can be reduced to a linear programming problem and solved with the help of e.g. the simplex algorithm, but no symbolic model checking is considered. Based on the algorithms of [5, 7], we derive symbolic model checking procedure for PBTL over concurrent probabilistic systems using MTBDDs, and extend it with fairness constraints. We furthermore implement an experimental model checker using the Colorado University Decision Diagram (CUDD) package [32]. Our key contribution is an implementation of the simplex algorithm in terms of MTBDDs.
Bisimulation Algorithms for Stochastic Process Algebras and their BDDbased Implementation
 In ARTS, LNCS 1601
, 1999
"... . Stochastic process algebras have been introduced in order to enable compositional performance analysis. The size of the state space is a limiting factor, especially if the system consists of many cooperating components. To fight state space explosion, various proposals for compositional aggregatio ..."
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Cited by 36 (13 self)
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. Stochastic process algebras have been introduced in order to enable compositional performance analysis. The size of the state space is a limiting factor, especially if the system consists of many cooperating components. To fight state space explosion, various proposals for compositional aggregation have been made. They rely on minimisation with respect to a congruence relation. This paper addresses the computational complexity of minimisation algorithms and explains how efficient, BDDbased data structures can be employed for this purpose. 1 Introduction Compositional application of stochastic process algebras (SPA) is particularly successful if the system structure can be exploited during Markov chain generation. For this purpose, congruence relations have been developed which justify minimisation of components without touching behavioural properties. Examples of such relations are strong equivalence [22], (strong and weak) Markovian bisimilarity [16] and extended Markovian bisimi...
Symbolic model checking for probabilistic processes using MTBDDs and the Kronecker representation
 In Tools and Algorithms for the Analysis and Construction of Systems, LNCS 1785
, 2000
"... Abstract. This paper reports on experimental results with symbolic model checking of probabilistic processes based on MultiTerminal Binary Decision Diagrams (MTBDDs). We consider concurrent probabilistic systems as models; these allow nondeterministic choice between probability distributions and ar ..."
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Cited by 34 (2 self)
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Abstract. This paper reports on experimental results with symbolic model checking of probabilistic processes based on MultiTerminal Binary Decision Diagrams (MTBDDs). We consider concurrent probabilistic systems as models; these allow nondeterministic choice between probability distributions and are particularly well suited to modelling distributed systems with probabilistic behaviour, e.g. randomized consensus algorithms and probabilistic failures. As a specification formalism we use the probabilistic branchingtime temporal logic PBTL which allows one to express properties such as “under any scheduling of nondeterministic choices, the probability of φ holding until ψ is true is at least 0.78/at most 0.04 ”. We adapt the Kronecker representation of (Plateau 1985), which yields a very compact MTBDD encoding of the system. We implement an experimental model checker using the CUDD package and demonstrate that model construction and reachabilitybased model checking is possible in a matter of seconds for certain classes of systems consisting of up to 10 30 states. 1
Power Estimation in Sequential Circuits
, 1995
"... A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences to the circuit, statistics on the latch outputs are collected, by simulation, that allow efficient power estimation for the whole ..."
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Cited by 30 (6 self)
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A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences to the circuit, statistics on the latch outputs are collected, by simulation, that allow efficient power estimation for the whole design. An important advantage of this approach is that the desired accuracy can be specified upfront by the user; the algorithm iterates until the specified accuracy is achieved. This has been implemented and tested on a number of sequential circuits and found to be much faster than existing techniques. We can complete the analysis of a circuit with 1,452 flipflops and 19,253 gates in about 4.6 hours (the largest test case reported previously has 223 flipflops). I. INTRODUCTION The dramatic decrease in feature size and the corresponding increase in the number of devices on a chip, combined with the growing demand for portable communication and computing systems, have made power consump...