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...also reduce simulator complexity and development time. 7.3 FPGA-accelerated simulation Another approach that has gained interest recently is to accelerate simulation by mapping timing models on FPGAs =-=[6, 29, 24]-=-. The timing models in FPGA-accelerated simulators are typically cycle-accurate, with the speedup coming from the fine-grained parallelism in the FPGA. A key challenge for FPGA-accelerated simulation ...

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...ailed memory model which does not include cache-coherence. They have a perfect core model which only stalls due to cache misses, and their network model comprises of a magic crossbar. Pellauer et. al =-=[25]-=- have recently developed a multicore simulator on FPGAs with detailed core and network models. Making use of time multiplexing, the largest system that they have demonstrated on a single FPGA chip com...

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...up system execution. Although FPGA resources constrain the size of design one can implement, recent advances in FPGA-based design methodologies have shown that such constraints can be overcome. HAsim =-=[18]-=-, for example, has shown using its time multiplexing technique how one can model a shared-memory multicoresystem including detailed core pipelines, cache hierarchy, and on-chip network, on a single F...

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...d information about the NoC topology and determine the proper set of buffers to be used by the currently simulated router. Time-multiplexing and Network Simulation. As has been shown in previous work =-=[5]-=-, [6], time-multiplexing in the context of network simulation requires special care to retain proper ordering of events and careful state management to ensure that all routers in the network have a co...

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... is to simulate a limited, but representative number of simulation points [8, 25, 32]. Another approach that has gained interest recently is to accelerate simulation by mapping timing models on FPGAs =-=[22, 29]-=-. The timing models in FPGA-accelerated simulators are typically cycle-accurate, with the speedup coming from the fine-grained parallelism in the FPGA. Higher abstraction simulation, as employed in Sn...

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...used in many contexts to develop large hardware systems such as processor designs [31], video decoders [45], kernel accelerators [33], cache coherence engines [34], hardwarebased processor simulators =-=[41, 72]-=-, and wireless basebands [67]. These have leveraged Guarded Atomic Actions to reduce code size, increase modularity and design flexibility, and reduce design time. These projects have shown that Guard...

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...up system execution. Although FPGA resources constrain the size of design one can implement, recent advances in FPGA-based design methodologies have shown that such constraints can be overcome. HAsim =-=[131]-=-, for example, has shown using its time multiplexing technique how one can model a shared-memory multicore system including detailed core pipelines, cache hierarchy, and on-chip network, on a single F...

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...s (aka guarded atomic actions). The main benefits of Bluespec HDL are: − strong type checking, − polymorphism (like in C++ templates), − built -in h igh-level modules (e.g. FIFO), − integration with Verilog and VHDL RTL. The Bluespec compiler transforms source code into high-quality Verilog RTL, which can be further synthesized into net lists using well-known industrial CAD tools such as Synopsys Synplify Pro or Xilinx ISE. 2.3. The HAsim Framework HAsim is a framework for FPGA -based cycle-accurate microprocessor simulators jo intly developed by Intel and Massachusetts Institute of Technology[7]. HAsim offers a method for writing t iming models that run on FPGAs, using programming techniques similar to software-based timing models. It decreases development effort p roviding a LEAP virtual p latform, a set of interfaces for FPGA applicat ion with a consistent set of useful services and device abstractions, a memory hierarchy and a flexib le RRR (Remote Request-Response) asynchronous communicat ion protocol across a range of physical FPGA platforms. However, the original HAsim methodology uses top-down design flow and doesn’t provide methods and tools for independent unit-level develop...

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...a high amount of communication among parallelized activities occurs across simulation cycles, which is hard to manage efficiently using typical communication methods such as shared memory. 2.3.2 FPGA-Based Models Addressing the simulation speed problem of software-based full-system simulators, some FPGA-based models have been proposed. However, most of them do not support detailed NoC models and can scale to only several tens of cores. RAMP Gold [38] can emulate up to 64 SPARC cores (without a detailed model of NoC interconnect) on a Virtex-5 FPGA, but with some compromises on accuracy. HAsim [39] and Heracles [40] use NoC for the communication fabric, but the number of cores that can be emulated is less than 32. Several many-core emulators such as Arete [41] are built using multiple FPGAs. However, this approach leads to much more complex designs. Moreover, the off-chip communication between FPGAs restricts performance of the entire system. DART [14] is an FPGA-based NoC emulator supporting both trace-driven workloads and synthetic workloads. DART provides a global interconnect between all nodes. With the global interconnect, by configuring the routing tables appropriately using a sof...