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**1 - 3**of**3**### Semiconductors

, 2011

"... During the study week 2011 we worked on the question of how to automate certain aspects of the design of analog chips. Here we focused on the task of connecting different blocks with electrical wiring, which is particularly tedious to do by hand. For digital chips there is a wealth of research avail ..."

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During the study week 2011 we worked on the question of how to automate certain aspects of the design of analog chips. Here we focused on the task of connecting different blocks with electrical wiring, which is particularly tedious to do by hand. For digital chips there is a wealth of research available for this, as in this situation the amount blocks makes it hopeless to do the design by hand. Hence, we set our task to finding solutions that are based on the previous research, as well as being tailored to the specific setting given by NXP. This resulted in a heuristical approach, which we presented at the end of the week in the form of a protoype tool. In this report we give a detailed account of the ideas we used, and describe possibilities to extend the approach. 1

### Minimum d-dimensional arrangement with fixed points

, 2014

"... In the Minimum d-Dimensional Arrangement Problem (d-dimAP) we are given a graph with edge weights, and the goal is to find a 1-1 map of the vertices into Zd (for some fixed dimension d ≥ 1) minimizing the total weighted stretch of the edges. This problem arises in VLSI placement and chip design. Mot ..."

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In the Minimum d-Dimensional Arrangement Problem (d-dimAP) we are given a graph with edge weights, and the goal is to find a 1-1 map of the vertices into Zd (for some fixed dimension d ≥ 1) minimizing the total weighted stretch of the edges. This problem arises in VLSI placement and chip design. Motivated by these applications, we consider a generalization of d-dimAP, where the positions of some of the vertices (pins) is fixed and specified as part of the input. We are asked to extend this partial map to a map of all the vertices, again minimizing the weighted stretch of edges. This generalization, which we refer to as d-dimAP+, arises naturally in these application domains (since it can capture blocked-off parts of the board, or the requirement of power-carrying pins to be in certain locations, etc.). Perhaps surprisingly, very little is known about this problem from an approximation viewpoint. For dimension d = 2, we obtain an O(k1/2 · log n)-approximation algorithm, based on a strength-ening of the spreading-metric LP for 2-dimAP. The integrality gap for this LP is shown to be Ω(k1/4). We also show that it is NP-hard to approximate 2-dimAP+ within a factor better than Ω(k1/4−ε). We also consider a (conceptually harder, but practically even more interesting) variant of 2-dimAP+, where the target space is the grid Z√n ×Z√n, instead of the entire integer lattice Z2. For this prob-lem, we obtain a O(k · log2 n)-approximation using the same LP relaxation. We complement this upper bound by showing an integrality gap of Ω(k1/2), and an Ω(k1/2−ε)-inapproximability result. Our results naturally extend to the case of arbitrary fixed target dimension d ≥ 1.