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Generating Synthetic Benchmark Circuits for Evaluating CAD Tools
, 2000
"... For the development and evaluation of CADtools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable characteristic parameters is required. Observing the lack of industrial benchmark circuits available for use in evaluation too ..."
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Cited by 35 (9 self)
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For the development and evaluation of CADtools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable characteristic parameters is required. Observing the lack of industrial benchmark circuits available for use in evaluation tools, one could consider to actually generate synthetic circuits. In this paper, we extend a graphbased benchmark generation method to include functional information. The use of a userspecified component library, together with the restriction that no combinational loops are introduced, now broadens the scope to timingdriven and logic optimizer applications. Experiments show that the resemblance between the characteristic Rent curve and the net degree distribution of real versus synthetic benchmark circuits is hardly influenced by the suggested extensions and that the resulting circuits are more realistic than before. An indirect validation verifies that existing partitioning programs have comparable behavior for both real and synthetic circuits. The problems of accounting for timingaware characteristics in synthetic benchmarks are addressed in detail and suggestions for extensions are included.
Recent Advances in SystemLevel Interconnect Prediction
 IEEE Circuits and Systems Newsletter
, 2000
"... The exciting, new field of SystemLevel Interconnect Prediction emerged from research of the early 1970's but it took until 1999 before a cohesive research community for interconnect prediction was established. New research results are becoming available and the last couple of years have brou ..."
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Cited by 5 (1 self)
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The exciting, new field of SystemLevel Interconnect Prediction emerged from research of the early 1970's but it took until 1999 before a cohesive research community for interconnect prediction was established. New research results are becoming available and the last couple of years have brought both more interest and more progress in the field than in the thirty years before. This paper is an introduction to the field and provides an overview of some of the recent advances in systemlevel interconnect prediction. 1 Introduction As mainstream processors surpass gigahertz global clock frequencies and new design and process technologies enable even higher performance, much attention is directed toward managing the influence of interconnects in deep submicron designs. Today, interconnects are the limiting factor for both performance and density, i.e., the value and the cost of the VLSI system. Guided by better models of interconnect performance at the atomistic and grain levels of...
A Stochastic Model for Interconnection Complexity based on Rent's Rule
, 2000
"... In the past, Rent's rule has been successfully applied for a priori estimation of wire length distributions. Deviations to Rent's rule appear due to the existence of heterogeneity. This can be classified in hierarchical and spatial heterogeneity. Stochastic models for the interconnection c ..."
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Cited by 4 (2 self)
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In the past, Rent's rule has been successfully applied for a priori estimation of wire length distributions. Deviations to Rent's rule appear due to the existence of heterogeneity. This can be classified in hierarchical and spatial heterogeneity. Stochastic models for the interconnection complexity, based on Rent's rule, are introduced. A coarse model shows that the variance follows a power law relationship. A more refined model incorporates the effect of local spatial heterogeneity. Experiments show that this is sufficient to model the variance of the terminal count distribution. Finally, the model is further extended to incorporate global spatial heterogeneity.
Multiterminal Nets do Change Conventional Wire Length Distribution Models
 Trans. Amer. Math. Soc
, 2001
"... Conventional models for estimating wire lengths in computer chips use Rent's rule to estimate the number of terminals between sets of gates. The number of interconnections then follows by taking into account that most nets are pointto point connections. In this paper, we introduce a model for ..."
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Cited by 3 (1 self)
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Conventional models for estimating wire lengths in computer chips use Rent's rule to estimate the number of terminals between sets of gates. The number of interconnections then follows by taking into account that most nets are pointto point connections. In this paper, we introduce a model for multiterminal nets and we show that such nets have a fundamentally different influence on the wire length estimations than pointtopoint nets. The multiterminal net model is then used to estimate the wire length distribution in two cases: (i) the distribution of sourcesink pairs for applications of delay estimation and (ii) the distribution of Steiner tree lengths for applications related to routing resource estimation. The effects of including multiterminal nets in the estimations are highlighted. Experiments show that the new estimated wire length distributions are close to the measured ones. Keywords Wire length estimation, Multiterminal nets, Rent's rule. 1.
Pin Balancing in Ratio Cut Partitioning
 Proc. Swiss Conf. on CAD/CAM
, 1999
"... Partitioning is a fundamental step in the computeraided design process. One of the best algorithms for partitioning is ratio cut [10] but, as many others, it does not take into account specific properties of multiterminal nets, especially with regard to module pin count. In this paper, we show that ..."
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Cited by 1 (1 self)
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Partitioning is a fundamental step in the computeraided design process. One of the best algorithms for partitioning is ratio cut [10] but, as many others, it does not take into account specific properties of multiterminal nets, especially with regard to module pin count. In this paper, we show that the number of pins per module can be unbalanced if not taken care of properly. Since this unbalance can have important implications, we present a way to improve the pin balance without losing the best partitioning qualities. Keywords: Partitioning, Ratio cut, Balanced pin count, Multiterminal nets, Rent's rule. 1 Introduction The production of VLSI and ULSI 1 computer chips requires the layout (partitioning, placement and routing) of the chip design on a carrier. The huge amount of components in presentday circuits requires a partitioning of the circuit into smaller modules. This partitioning step is necessary for being able to cope with the "size" of the circuit in the next layout s...
RATIO CUT HYPERGRAPH PARTITIONING USING BDD BASED MBOA OPTIMIZATION ALGORITHM
"... Abstract. This paper deals with the kway ratio cut hypergraph partitioning utilizing the Mixed discrete continuous variant of the Bayesian Optimization Algorithm (mBOA). We have tested our algorithm on three partitioning taxonomies: recursive minimum ratio cut, multiway minimum ratio cut and recur ..."
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Abstract. This paper deals with the kway ratio cut hypergraph partitioning utilizing the Mixed discrete continuous variant of the Bayesian Optimization Algorithm (mBOA). We have tested our algorithm on three partitioning taxonomies: recursive minimum ratio cut, multiway minimum ratio cut and recursive minimum cut bisection. We have also derived a new approach for modeling of Boolean functions using binary decision diagrams (BDDs) which are primarily used as a probabilistic model of the mBOA algorithm. 1
BAYESDIRICHLET BDD AS A PROBABILISTIC MODEL FOR LOGIC FUNCTION AND EVOLUTIONARY CIRCUIT DECOMPOSER Josef
"... Abstract: This paper deals with the utilizing of Binary Decision Diagrams built on the BayesDirichlet metric for representation of logic functions. In the first phase the Binary Decision Tree is built followed by a reduction process resulted in binary decision diagram (BDD). The BDDs are also used ..."
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Abstract: This paper deals with the utilizing of Binary Decision Diagrams built on the BayesDirichlet metric for representation of logic functions. In the first phase the Binary Decision Tree is built followed by a reduction process resulted in binary decision diagram (BDD). The BDDs are also used as a probabilistic model for advanced Bayesian decomposer for digital circuit partitioning. It is shown that this approach is more efficient than the utilizing of Bayesian networks (BN) and in addition the concept of BDDs parallelization is simple to implement. Key Words:. Logic function, binary decision diagrams, BayesDirichlet metric, digital circuit partitioning. 1