Abstract—Networks-on-Chip are seen as promising interconnect solutions, offering the advantages of scalability and high frequency operation which the traditional bus interconnects lack. Several NoC implementations have been presented in the literature, some of them having mature tool-flows. The main differentiating factor between the various implementations are the services and communication patters they offer to the end-user. In this paper we present dAElite, a TDM Network-on-Chip that offers a unique combinations of features, namely guaranteed bandwidth and latency per connection, built-in support for multicast, and a short connection set-up time. While our NoC was designed from the ground up, we leverage on existing tools for network dimensioning, analysis and instantiation. We have implemented and tested our proposal in hardware and we compared it to Æthereal, a state-of-the-art NoC with similar features, but no multicast. We find that the connection set-up time is reduced by a factor of 10 and the network traversal latency is decreased by 33%. Moreover, considering realistic values of the network parameters dAElite has a lower hardware area when synthesized in 65 nm technology.

The objective of this paper is to introduce the impact of faulty links on Quality of Service in Network-on-Chip (NoC) under different traffic pattern. NoC paradigm has made it possible to concurrently run multiple applications on IP-core based System on Chip. It is therefore necessary to predict the multi-processor systems-on-chip communication, which is a critical issue and needs to be addressed by the right mix of soft and hard real-time guarantees. To meet this requirement state of the art packet switched NoC provide different levels of quality of service (QoS) such as best effort (BE) and guaranteed throughput (GT). This paper presents a novel scheme which compares and evaluates the performance of guaranteed throughput and best effort traffic in Network-on-Chip under different synthetic traffic generators and highlights its dependence in terms of latency on the type of traffic patterns and number of link failures for mesh topology. It also explores the effect of robustness of a particular traffic pattern in terms of fault tolerance (variation in average latency as the number of link failures increases) for planar adapter routing function on latency of GT and BE traffic class for mesh topology. Key words: