In this paper, we introduce a precise energy characterization of SDRAM main memory systems and explore the amount of energy associated with design parameters, leading to energy reduction techniques that we are able to recommend for practical use.

Abstract- We present an effective power mode management scheme used in SDRAM memory controllers. The scheme employs a bus utilization monitoring mechanism to initiate proper operations of SDRAM chips. Our approach reduces energy consumption by actively switching memories to low-power mode at low bus utilization. At higher bus utilization, the scheme switches memories to open page mode to reduce precharge energy as well as program execution time. This bus utilization predictor reduces memory energy consumption without the expense of increasing program execution time. It achieved the performance level of open page policy by consuming 20 % less of memory energy. I.

Abstract — To increase the bandwidth of synchronous memories that are widely adopted for HDTV decoder systems, a predictive mode control scheme is proposed in this paper. Memory latency and energy consumption can be reduced by effectively managing the states of banks. The local access history of each bank is considered to predict the memory mode. In a HDTV decoder system, experimental results show that the proposed scheme reduces the memory latency and the energy consumption by 18.8 % and 23.3%, respectively, over the conventional scheme that always keeps the memory in idle state. A hardware architecture and its VLSI implementation are also presented 1. Index Terms — HDTV decoder, History-based prediction, memory controller, memory performance, synchronous memory. I.

To increase the bandwidth of synchronous memories that are widely adopted for high performance memory systems, a predictive mode control scheme is proposed to reduce memory latency by effectively managing the states of banks. The local access history of each bank is considered to predict the memory mode. Experimental results show that the proposed scheme, at the cost of negligible area overhead, reduces the memory latency by 19.0 % over the conventional scheme that always keeps the memory in idle state. 1.

Modern processors are experiencing interleaved memory access streams from different threads/cores, reducing the spatial locality that is seen at the memory controller, making the combined stream appear increasingly random. Traditional methods for exploiting locality at the DRAM level, such as open-page and timer-based policies, become less effective as the number of threads accessing memory increases. Employing closed-page policies in such systems can improve performance but it eliminates any possibility of exploiting locality. In this paper, we build upon the key insight that a history-based predictor that tracks the number of accesses to a given DRAM page is a much better indicator of DRAM locality than timer based policies. We extend prior work to propose asimpleAccess Based Predictor (ABP)that tracks limited access history at the page level to determine page closure decisions, and does so with much smaller storage overhead than previously proposed policies. We show that ABP, with additional optimizations, can improve system throughput by 12.3 % and 21.6 % over open and closedpage policies, respectively. The proposed ABP requires 20 KB of storage overhead and is outside the critical path of memory access. Keywords-DRAM row-buffer managagement; predictor; I.