In the past decade, the proliferation of mobile devices has increased at a spectacular rate. There are now more than 3.3 billion active cell phones in the world—a device that we now all depend on in our daily lives. The current generation of devices employs a combination of general-purpose processors, digital signal processors, and hardwired accelerators to provide giga-operations-per-second performance on milliWatt power budgets. Such heterogeneous organizations are inefficient to build and maintain, as well as waste silicon area and power. Looking forward to the next generation of mobile computing, computation requirements will increase by one to three orders of magnitude due to higher data rates, increased complexity algorithms, and greater computation diversity but the power requirements will be just

Abstract-This paper presents a programmable many-core platform containing 64 cores routed in a hierarchical network tor biomedical signal processing applications. Individual core processors are based on a RISC architecture with DSP enhance ment blocks. Given the number of conditional program loops in DSP applications such as FFT, additional hardware blocks are added that operate in parallel to each core processor. The two blocks calculate the FFT input addresses and determine if a conditional loop is necessary. Pertorming these operations in parallel to the main processor greatly reduces the time to completion for a DSP application. Each processor is implemented in 65 nm CMOS using standard cell Iibraries. The 64-core platform occupies 19.51 mm2 and runs at 1.18 GHz at 1 V. For demonstration, Electroencephalogram (EEG) seizure detection and analysis and uItrasound spectral doppler are mapped onto the cores. The seizure detection and analysis algorithm utilizes 60 processors and takes 890 ns to execute. Spectral doppler utilizes 29 processors and takes 715 ns to run. Index Terms-65 nm CMOS, DSP, many-core, biomedical signal processing, seizure detection, uItrasound

One central challenge in the realization of Software Defined Radio (SDR) is to provide a programmable solution that meets the challenging high-performance, low-power requirements, while providing an efficient software development interface. In this paper, we present an overview of a fully programmable multi-core SIMD architecture for SDR. Our solution can support 2Mbps W-CDMA at about 270mW, and 24Mbps 802.11a at about 370mW in 90nm technology. This high computational efficiency is achieved by exploiting the vector characteristics of the algorithms, through a unique multi-core architecture that consists of tightly coupled scalar and wide SIMD pipelines. In addition, we present a software design flow that supports efficient DSP programming and implementation through a set of signal processing extensions to C, referred to as SPEX.

This dissertation would not have been possible without the guidance and support of many people. First, and foremost, I would like to give thanks to my advisor, Professor Trevor Mudge. Throughout my Ph.D. he has given me support and encour-agement through thick and thin. His guidance has helped me overcome many hurdles that i have encountered. Without him, this dissertation would not be possible. I would also like to thank Professors Scott Mahlke and Chaitali Chakrabarti. Without their tireless effort and help, my research would not be possible. Both have put in countless hours to develop ideas and help complete my research. I would like to thank ARM Ltd and especially Krisztian Flautner for not only funding my research but also providing me with the valuable insight that has gotten me this far. Without the their trust and confidence in my work, I would not have gotten this far. I would also like to thank my thesis committee members, Professors David Blaauw and William Martin. They have given their time and provided me with valuable insights which have helped me improve my thesis. The research presented in this dissertation also would not be possible without the ii support and encouragement of many of my colleagues. In particular, Dr. Yuan Lin, Dr. Sangwon Seo and Dr. Hyunseok Lee have assisted me in virtually every aspect of my graduate school life: running experiments, refining ideas, writing papers, and even picking me up when i was stranded in Auburn Hills. I would also like to thank all of my colleagues in EECS. Many of whom I’ve discussed ideas with for countless hours. Their support not only as a colleague but also as a friend were crucial to my graduate school experience. I’d like to personally

Stream processing has emerged as an important model of computation especially in the context of multimedia and communication sub-systems of embedded System-on-Chip (SoC) architectures. The dataflow nature of streaming applications allows them to be most naturally expressed as a set of kernels iteratively operating on continuous streams of data. The kernels are computationally intensive and are mainly character-ized by real-time constraints that demand high throughput and data bandwidth with limited global data reuse. Conventional architectures fail to meet these demands due to their poorly matched execution models and the overheads associated with instruction and data movements. This work presents StreamWorks, a multi-core embedded architecture for energy-efficient stream computing. The basic processing element in the StreamWorks ar-chitecture is the StreamEngine (SE) which is responsible for iteratively executing a stream kernel. SE introduces an instruction locking mechanism that exploits the iter-ative nature of the kernels and enables fine-grain instruction reuse. Each instruction