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Generalized Disjunction Decomposition for Evolvable Hardware
- IEEE Transactions on Systems, Man, and Cybernetics – Part B
"... Abstract—Evolvable hardware (EHW) refers to selfreconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evo ..."
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Abstract—Evolvable hardware (EHW) refers to selfreconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the “generalized disjunction decomposition ” (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using the (1 + λ) evolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided. Index Terms—Adaptive system, evolutionary computation, evolvable hardware (EHW), problem decomposition. I.
A bird’s eye view of FPGA-based evolvable hardware
- in Adaptive Hardware and Systems (AHS), 2011 NASA/ESA Conference on, 2011
"... very important progresses in the last two decades. However, it is still quite far from being as revolutionary as depicted in the earlier visionary papers. To have a positive impact on the Embedded Design Automation field, Evolvable Hardware systems should start to deal with more complex problems ins ..."
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Cited by 5 (1 self)
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very important progresses in the last two decades. However, it is still quite far from being as revolutionary as depicted in the earlier visionary papers. To have a positive impact on the Embedded Design Automation field, Evolvable Hardware systems should start to deal with more complex problems instances efficiently. This paper describes some interesting results achieved so far in the Evolvable Hardware area and gives some hints on what should be done for increasing the efficiency of Evolvable Hardware systems. I.
Evolutionary Design of Digital Circuits: Where Are
- Current Limits”, First NASA/ESA Conference on Adaptive Hardware and Systems
, 2006
"... The objective of this paper is to classify the approaches proposed to the evolutionary digital circuit design in the recent years and to identify the levels of complexity and innovation that can be obtained by means of these ap-proaches. In particular, gate-level evolution, circuit evo-lution in PLA ..."
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The objective of this paper is to classify the approaches proposed to the evolutionary digital circuit design in the recent years and to identify the levels of complexity and innovation that can be obtained by means of these ap-proaches. In particular, gate-level evolution, circuit evo-lution in PLAs, functional-level evolution, incremental evo-lution, evolution utilizing developmental schemes and some application-specific schemes are analyzed. It is shown that we are able to effectively explore the search spaces not much larger than 21000 points and that the innovative solu-tions can be produced independently of the utilized method. 1
Robot Gaits Evolved by Combining Genetic Algorithms and Binary Hill Climbing
"... In this paper an evolutionary algorithm is used for evolving gaits in a walking biped robot controller. The focus is fast learning in a real-time environment. An incremental approach combining a genetic algorithm (GA) with hill climbing is proposed. This combination interacts in an efficient way to ..."
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In this paper an evolutionary algorithm is used for evolving gaits in a walking biped robot controller. The focus is fast learning in a real-time environment. An incremental approach combining a genetic algorithm (GA) with hill climbing is proposed. This combination interacts in an efficient way to generate precise walking patterns in less than 15 generations. Our proposal is compared to various versions of GA and stochastic search, and finally tested on a pneumatic biped walking robot. Categories and Subject Descriptors I.2.9 [Artificial Intelligence]: Robotics—Propelling mechanisms;
Improving flexibility in on-line evolvable systems by reconfigurable computing
- In Evolvable Systems: From Biology to Hardware. Seventh International Conference, ICES’07, volume 4684 of Lecture Notes in Computer Science
, 2007
"... Abstract. Reconfigurable logic is a promising technology for adaptable systems – often called reconfigurable computing. However, one of the main challenges with autonomous adaptable systems is the flexibility. The paper starts with giving an overview of reconfigurable computing and different approac ..."
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Abstract. Reconfigurable logic is a promising technology for adaptable systems – often called reconfigurable computing. However, one of the main challenges with autonomous adaptable systems is the flexibility. The paper starts with giving an overview of reconfigurable computing and different approaches to how it can be implemented. Then, we outline how these can be applied in on-line evolvable systems to improve flexi-bility in the hardware. The challenge of the latter is to include flexibility without re-synthesis and avoid having a too large logic gate overhead. An architecture based on system-on-chip and partial reconfiguration is proposed in the paper. 1
Algorithms
"... In this paper an evolutionary algorithm is used for evolving gaits in a walking biped robot controller. The focus is fast learning in a real-time environment. An incremental approach combining a genetic algorithm (GA) with hill climbing is proposed. This combination interacts in an efficient way to ..."
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In this paper an evolutionary algorithm is used for evolving gaits in a walking biped robot controller. The focus is fast learning in a real-time environment. An incremental approach combining a genetic algorithm (GA) with hill climbing is proposed. This combination interacts in an efficient way to generate precise walking patterns in less than 15 generations. Our proposal is compared to various versions of GA and stochastic search, and finally tested on a pneumatic biped walking robot.
Can Run-time Reconfigurable Hardware be more Accessible?
"... Abstract — In this paper, a new project named Context ..."
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Hardware genetic algorithm optimisation by critical path analysis using a custom VLSI architecture
, 2014
"... This paper investigates optimisation of Evolutionary Hardware Systems (EHW) by means of digital circuit critical path analysis. A 2×2 digital multiplier and a Finite State Machine (FSM) control circuit were evolved using a target-independent Virtual Reconfigurable Circuit (VRC) architecture. An in-d ..."
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This paper investigates optimisation of Evolutionary Hardware Systems (EHW) by means of digital circuit critical path analysis. A 2×2 digital multiplier and a Finite State Machine (FSM) control circuit were evolved using a target-independent Virtual Reconfigurable Circuit (VRC) architecture. An in-depth analysis of the phenotypes ’ Critical Paths (CP) was performed. Through analysing the CPs, it was shown that a great amount of insight can be gained into a phenotype’s fitness. Particularly, the identification of the CP’s dependence is valuable, since dependent CPs reduced the required net number of evolved Logic Elements (LE). Generally, in both the multiplier and state phenotypes, the CPs were evolved in ascending order of the net LEs. This suggests that evolution always favoured CPs with lower net numbers. However, we have seen that in one special case, if two independent CPs are used by a third CP, the resulting third CP has a lower net number than both independent CPs. The CP analysis also led to the development of the FitnessOverall fitness function, which had a distinctive way of not only rewarding correct output elements, but also encouraging more efficient evolution through sustaining evolved CPs, and further developing partially-evolved CPs. Finally, by using the optimized fitness function, we demonstrated the evolution of a FSM control circuit. The results verify that optimised GAs can find solutions quicker, and with fewer attempts.
1DGECS: Description Generator for Evolved Circuits Synthesis
"... Abstract — Evolvable Hardware (EHW) is an approach to the creation of hardware circuits based on a goal-oriented evolutionary process inspired by natural evolution. This approach allows the exploration of a very large design search space, ideally enabling to find solutions that are better in terms o ..."
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Abstract — Evolvable Hardware (EHW) is an approach to the creation of hardware circuits based on a goal-oriented evolutionary process inspired by natural evolution. This approach allows the exploration of a very large design search space, ideally enabling to find solutions that are better in terms of resource requirements, accuracy or timing performance, with respect to traditional design methods. To exploit this approach, it must be possible to port the evolved circuits to custom designs; however, in FPGA-based EHW systems (and, in particular, in the HERA project), the configuration bitstream for an evolved circuit is specific to the evolutionary platform and it cannot be ported to a different architecture. This paper expands the HERA framework with a tool able to export hardware circuits evolved within the HERA framework to an IP-core reusable in any PLB-based custom design. DGECS (Description Generator for Evolved Circuits Synthesis) permits to export evolved circuits to a VHDL description which can be then synthesized and plugged into a custom PLB architecture. Experimental results provide evidence that DGECS allows to correctly export evolved circuits; moreover, it enables to save resources thanks to the optimizations introduced by the synthesis flow it relies on. I.
