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Application-Specific Multiprocessor . . .
"... It often happens that designers have to integrate different instruction-set processors on a single chip. Typical applications are wireless, image processing, xDSL, network and game processors. This paper deals with the three main problems that make the design of application-specific heterogeneous mu ..."
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Cited by 126 (5 self)
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It often happens that designers have to integrate different instruction-set processors on a single chip. Typical applications are wireless, image processing, xDSL, network and game processors. This paper deals with the three main problems that make the design of application-specific heterogeneous multiprocessor Systems-on-Chip very hard and expensive: higher level specification; software support packages design; on-chip HW/SW communication design.
Design Space Exploration for Optimizing On-Chip Communication Architectures
- IEEE transactions on Computer-Aided Design of Integrated Circuits and Systems
, 2004
"... Rapid growth in the c,15552,( ofsystem-on-c94, is being acng,29063 byinc easing volume and diversity ofon-c31 c-c316 ccc trafficff,79 in turn,is driving the development of advanc2 system-level c058,(56100, arc,14521, es. While these arc,23587, es have the potential to improve system perfo ..."
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Cited by 40 (1 self)
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Rapid growth in the c,15552,( ofsystem-on-c94, is being acng,29063 byinc easing volume and diversity ofon-c31 c-c316 ccc trafficff,79 in turn,is driving the development of advanc2 system-level c058,(56100, arc,14521, es. While these arc,23587, es have the potential to improve system performanc99,(5 pose significni new cw,29066, to the system designer,owing to thece,200 designspac defined by the availability of numerous networktopologies,c12,c12,c protoc7,(525 mapping alternatives for systemctem,20373,(52 In this paper,we address the problem of mapping a system'sctem's,23426 requirements to a given c3095,(50724 arc,20263, e template. We illustrate the nature of the c,13740,(498 arc,20611, e design spacn anddesc245 an exploration methodology that uses effic,23 algorithms to help automate the proc12 of mapping the system ctem,23084,(4 to theselec90 template. In addition,we demonstrate the importanc of simultaneously optimizing theon-c57 cc5707,(462 protoc63 in order to maximize system performanc6 Experimentscxperime on example systems,inc(4444 ac14 forwarding unit of an ATMswitc8 indic8 that the proposedtecd,1319 aid inautomatic354 ctomatic35 ctomatic35 arc10172,( es that have high performanc4 For the systems wec,4889, ed,the solutions generated using our methodology had 53% superior performanc (on average),over those based on c, ventional arc,4712,( es and mapping approac,15 The algorithms used in the proposed methodology arec3130,(39065,c effic20107,( sc2 well with inc easing cing,7446,(3 arc,13897, ec7281,(38 .
System-on-Chip Environment: A SpecC-based Framework for Heterogeneous MPSoC
- Design,”
, 2008
"... The constantly growing complexity of embedded systems is a challenge that drives the development of novel design automation techniques. C-based system-level design addresses the complexity challenge by raising the level of abstraction and integrating the design processes for the heterogeneous syste ..."
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Cited by 37 (18 self)
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The constantly growing complexity of embedded systems is a challenge that drives the development of novel design automation techniques. C-based system-level design addresses the complexity challenge by raising the level of abstraction and integrating the design processes for the heterogeneous system components. In this article, we present a comprehensive design framework, the system-on-chip environment (SCE) which is based on the influential SpecC language and methodology. SCE implements a top-down system design flow based on a specify-explore-refine paradigm with support for heterogeneous target platforms consisting of custom hardware components, embedded software processors, dedicated IP blocks, and complex communication bus architectures. Starting from an abstract specification of the desired system, models at various levels of abstraction are automatically generated through successive step-wise refinement, resulting in a pin-and cycle-accurate system implementation. The seamless integration of automatic model generation, estimation, and verification tools enables rapid design space exploration and efficient MPSoC implementation. Using a large set of industrial-strength examples with a wide range of target architectures, our experimental results demonstrate the effectiveness of our framework and show significant productivity gains in design time.
Scalable and Flexible Cosimulation of SoC Designs with Heterogeneous Multi-Processor Target Architectures
- Proc. of Asia South Pacific Design Automation Conference
, 2001
"... In this paper, we present a cosimulation environment that provides modularity, scalability, and flexibility in cosimulation of SoC designs with heterogeneous multi-processor target architectures. Our cosimulation environment is based on an object-oriented simulation environment, SystemC. Exploiting ..."
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Cited by 28 (7 self)
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In this paper, we present a cosimulation environment that provides modularity, scalability, and flexibility in cosimulation of SoC designs with heterogeneous multi-processor target architectures. Our cosimulation environment is based on an object-oriented simulation environment, SystemC. Exploiting the object orientation in SystemC representation, we achieve modularity and scalability of cosimulation by developing modular cosimulation interfaces. The object orientation also enables mixed-level cosimulation to be easily implemented thereby the designer can have flexibility in trade off between simulation performance and accuracy. Experiments with an IS-95 CDMA cellular phone system design show the effectiveness of the cosimulation environment. 1
Multi-processor system design with ESPAM
- In Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis
, 2006
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A Generic Wrapper Architecture for Multi-Processor SoC Cosimulation and Design
, 2001
"... In communication refinement with multiple communication protocols and abstraction levels, the system specification is described by heterogeneous components in terms of communication protocols and abstraction levels. To adapt each heterogeneous component to the other part of system, we present a gene ..."
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Cited by 24 (9 self)
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In communication refinement with multiple communication protocols and abstraction levels, the system specification is described by heterogeneous components in terms of communication protocols and abstraction levels. To adapt each heterogeneous component to the other part of system, we present a generic wrapper architecture that can adapt different protocols or different abstraction levels, or both. In this paper, we give a detailed explanation of applying the generic wrapper architecture to mixed-level cosimulation. As preliminary experiments, we applied it to mixed-level cosimulation of an IS-95 CDMA cellular phone system. 1
An Optimal Memory Allocation for Application-Specific Multiprocessor System-on-Chip
- in Proc. Intl. Symp. on System Synthesis
, 2001
"... In this paper, we present a novel and systematic approach for the design of shared memory architectures in the case of applicationspecific multiprocessor system-on-chip. This paper focuses on a memory allocation step which is based on an integer linear programming model. It permits to obtain an ..."
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Cited by 23 (2 self)
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In this paper, we present a novel and systematic approach for the design of shared memory architectures in the case of applicationspecific multiprocessor system-on-chip. This paper focuses on a memory allocation step which is based on an integer linear programming model. It permits to obtain an optimal distributed shared memory architecture minimizing the global cost to access the shared data in the application, and the memory cost. Our approach allows automatic generation of an architecture-level specification of the application. The effectiveness of this approach is illustrated by a packet routing switch example.
Automatic Generation of Embedded Memory Wrapper for Multiprocessor SoC
, 2002
"... Embedded memory plays a critical role to improve performances of systems-on-chip (SAC). In this paper, we present a new methodology for embedded memory design in the case of application specific multiprocessor system-on-chip. This approach facilitates the integration of standard memory components. T ..."
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Cited by 21 (1 self)
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Embedded memory plays a critical role to improve performances of systems-on-chip (SAC). In this paper, we present a new methodology for embedded memory design in the case of application specific multiprocessor system-on-chip. This approach facilitates the integration of standard memory components. The concept of memory wrapper allows automatic adaptation of physical memory interfaces to a communication network that may have a different number of access ports. We give also a generic architecture to produce this memory wrapper. This approach has successfully been applied on a lowlevel image processing application.
Automated Bus Generation for Multiprocessor SoC Design
, 2003
"... The performance of a system, especially a multiprocessor system, heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custom bus system for a multiprocessor System-on-a-Chip (SoC). Our bus synthesis tool (BusSyn) uses this methodology to genera ..."
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Cited by 21 (0 self)
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The performance of a system, especially a multiprocessor system, heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custom bus system for a multiprocessor System-on-a-Chip (SoC). Our bus synthesis tool (BusSyn) uses this methodology to generate five different bus systems as examples: Bi-FIFO Bus Architecture (BFBA), Global Bus Architecture Version I (GBAVI), Global Bus Architecture Version III (GBAVIII), Hybrid bus architecture (Hybrid) and Split Bus Architecture (SplitBA). We verify and evaluate the performance of each bus system in the context of two applications: an Orthogonal Frequency Division Multiplexing (OFDM) wireless transmitter and an MPEG2 decoder. This methodology gives the designer a great benefit in fast design space exploration of bus architectures across a variety of performance impacting factors such as bus types, processor types and software programming style. In this paper, we show that BusSyn can generate buses that achieve superior performance when compared to a simple General Global Bus Architecture (GGBA) (e.g., 16.44% performance improvement in the case of OFDM transmitter) or when compared to the CoreConnect Bus Architecture (CCBA) (e.g., 15.54% peformance improvement in the case of MPEG2 decoder). In addition, the bus architecture generated by BusSyn is designed in a matter of seconds instead of weeks for the hand design of a custom bus system.
