Results 1 -
5 of
5
BEAR-FP: A Robust Framework for Floorplanning
- INTERNATIONAL JOURNAL OF HIGH SPEED ELECTRONICS
, 1992
"... This paper presents a hierarchical floorplanning approach for macrocell layouts which is based on the bottom-up clustering, shape function computation, and top down floorplan optimization with integrated global routing and pin assignment. This approach provides means for specifying and techniques fo ..."
Abstract
-
Cited by 7 (2 self)
- Add to MetaCart
(Show Context)
This paper presents a hierarchical floorplanning approach for macrocell layouts which is based on the bottom-up clustering, shape function computation, and top down floorplan optimization with integrated global routing and pin assignment. This approach provides means for specifying and techniques for satisfying a wide range of constraints (physical, topological, timing) and is, therefore, able to generate floorplans for a number of different layout styles. A systematic and efficient optimization procedure during the selection of suitable floorplan patterns that integrates floorplanning, global routing and pin assignment, a new pin assignment technique based on linear assignment and driven by the global routing solution and floorplan topology, and an effective timing-driven floorplanning scheme are among the other novel features of the floorplanner. These techniques have been incorporated in BEAR-FP, a macro-cell layout system developed at the University of California, Berkeley. Results on various placement and floorplanning benchmarks are quite good.
Floorplanning with pin assignment
- In Proceedings of the IEEE International Conference on Computer Aided Design
, 1990
"... We present a hierarchical technique for floorplanning and pin assignment of the general cell layouts. Given a set of cells with their shape lists, a layout aspect ratio, relative positions of the extemal 110 pads and upper bound delay constraints for a set of critical nets, we determine shapes and p ..."
Abstract
-
Cited by 6 (2 self)
- Add to MetaCart
(Show Context)
We present a hierarchical technique for floorplanning and pin assignment of the general cell layouts. Given a set of cells with their shape lists, a layout aspect ratio, relative positions of the extemal 110 pads and upper bound delay constraints for a set of critical nets, we determine shapes and positions of the cells, locations of the floating pins on cells and a global routing solution such that a linear combination of the layout area, the total interconnection length and constraint violations for critical nets is minimized. Floorplanning, pin assignment and global routing influence one another during the hierarchical steps of the algorithm. The pin assignment algorithm is flexible and allows various user specified constraints such as pre-specified pin locations, feedthrough pins, length-critical nets and planar net topologies. Placement, timing and floorplanning results for Xerox general cell benchmark are reported. 1
Par-POPINS: A Timing-Driven Parallel Placement Method with the Elmore Delay Model for Row Based VLSIs
- Proc. Asia and South Pacific Design Automation Conf
, 1997
"... Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs ..."
Abstract
-
Cited by 5 (0 self)
- Add to MetaCart
(Show Context)
Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs
Enhancing and Using an Automatic Design System for Creating FPGAs
, 2005
"... The creation of integrated circuits has progressed from custom design and layout to the less time-intensive implementation media of ASICs and FPGAs. FPGAs provide the lowest development cost and fastest development time; however, the design of the FPGA itself is still a time-consuming, expensive, cu ..."
Abstract
-
Cited by 1 (0 self)
- Add to MetaCart
(Show Context)
The creation of integrated circuits has progressed from custom design and layout to the less time-intensive implementation media of ASICs and FPGAs. FPGAs provide the lowest development cost and fastest development time; however, the design of the FPGA itself is still a time-consuming, expensive, custom layout task that takes at least 50 person-years to complete. This work explores new techniques to automate the design and layout of FPGAs. An existing automatic layout system is improved by changing the grouping of transistors that form the basic building blocks of the system. These improvements result in a 16.8 % area savings over previous versions and only a 36% area increase compared to equivalent custom designs. The system was also extended to create the first automatic layout of an FPGA from a generic architecture description. These improvements and additions suggest that the automatic layout system is a viable alternative to custom layout of FPGAs. ii Acknowledgements I would like to thank my supervisor, Professor Jonathan Rose, for his advice and guidance in all aspects of this work and my education. Also, Ian Kuon deserves my profound thanks and gratitude for his achievements and co-operation that led to the completion of this work. This work would not have been possible without the people who worked on it
An Accurate and Stochastic-Based Approach to Timing-Driven Partitioning and Placement
"... We present an accurate new approach to timing-driven partitioning and placement that is particularly suited to deep submicron technology, and to the large circuits that are implemented on such chips. We present rationale for why iterative-improvement based partition-driven placement should be the ap ..."
Abstract
- Add to MetaCart
(Show Context)
We present an accurate new approach to timing-driven partitioning and placement that is particularly suited to deep submicron technology, and to the large circuits that are implemented on such chips. We present rationale for why iterative-improvement based partition-driven placement should be the approach of choice for optimizing any objective like timing, power and area. We establish desirable characteristics for the nodegain function of such a placement approach for timing minimization, and then show how previous techniques have been deficient in them. These drawbacks are remedied in our proposed approach, which is expected to be faster and more effective than current techniques. The speed increase will derive partly from the fact that our method is partition-driven, which, being a divide-and-conquer technique, is much faster than numerical or statistical (e.g., simulated annealing) methods. Our technique's increased effectiveness will result from our more accurate modeling of net co...
