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...tates in a finite-state machine or number of cubes in a minimum sum-of-products expression of a Boolean function, and circuit entropy) and technology/library information. Interconnect complicates the problem even more as it plays an increasingly important role in determining the capacitive loading of gates while its estimation is a very difficult task even after technology mapping due to lack of detailed place and route information. Approximate estimates can be obtained by using information derived from a companion placement solution [110] or by using stochastic/procedural interconnect models [108]. Interconnect capacitance estimation after layout is straight-forward and in general accurate. With this understanding, we can now consider how to reduce physical capacitance. We recognize that capacitances can be kept at a minimum by using less logic, smaller devices, fewer and shorter wires. Example techniques for reducing the active area include resource sharing, logic minimization and gate sizing. Example techniques for reducing the interconnect include register sharing, common sub-function extraction, placement and routing. As with voltage, however, we are not free to optimize capacitanc...

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... Gamal [12], Heller [8], Kurdahi [27] and Sastry [35]. We note that other authors have proposed wire length distribution models which do not use Rent's rule. These include Sechen[39], Pedram and Preas=-=[33]-=-, and Hamada et al.[19], all of whom estimate interconnection length based on local neighborhood analysis approaches: each signal net is propagated to random pin locations within a rectangular grid wh...

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...vant to certain design methodologies, but we are more concerned with early and fast predictions that afford the leverage essential to forward synthesis. mating channel height in standard-cell layouts =-=[13] [14]-=-, choosing between two competing placements, etc. Again, such estimates must be faster than actual construction of the routing. (Note that accuracy need not be perfect if the estimate has good "f...

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...tailed place and route information. Approximate estimates can be obtained by using information derived from a companion placement solution [49] or by using stochastic / procedural interconnect models =-=[50]-=-. Interconnect capacitance estimation after layout is straight-forward and in general accurate. With this understanding, we can now consider how to reduce physical capacitance. From the previous discu...

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...larly modeled.) The net length distribution for a given net weight was determined to be a gamma distribution. 4.2 Circuit Congestion The slopes of mean length and variance length vs. net weight are different for different designs, and incremental changes to the circuit topology do not overtly affect the slopes. The slopes were therefore assumed to be a function of the overall interconnect density or congestion of a circuit. A good measure of the congestion is the neighborhood population of a circuit. The concept of neighborhood population has been used previously to model interconnect lengths [15] and is defined here in the following way. Let Distance(cell1,cell2) be the number of cells traversed in the shortest path between cells 1 and 2 (in Fig. 4, Distance(a,g)=3). The neighborhood population of a cell at level i, Ngh(cell)i, is the number of cells residing within a distance i from the cell (in Fig. 4, Ngh(d)1=|{c,e,f,g,h}|=5, and Ngh(d)2=|{a,b}|=2). The total neighborhood population at level i, Anghi, is the sum of the neighborhood populations for all cells at level i (in Fig. 4, Angh1=22). An analysis of standard cell designs show that the slope of the mean of the net length vs. n...