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...ch as the rectifier area consumption and its parasitic capacitance will permit us to lower the dropout voltage. Figure 6. The diagram of the standard CMOS rectifier. A capacitor-less LDO architecture =-=[26]-=- is presented in this section as depicted in Figure 7. It is composed of bandgap voltage reference, error amplifier, pass transistor, feedback network and a compensation circuit. Figure 7. The structu...

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...rectly connected to the power transistor, itsmust be designed to rapidly charge (or discharge) thescapacitive contribution seen at the gate of MP that, quite often,smay be as large as 50 pF to 100 pF =-=[17]-=-. On the contrary, thesEA itself should provide very low power dissipation (especiallysin stand-by mode), and its bias currents must be kept as low asspossible. It is apparent that a speed/dissipation...

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...but the zero comessbefore the pole so still enough phase margin can be achieved. Some otherscompensation techniques have also been investigated to achieve stability evenswithout output capacitors. In =-=[67]-=-, people utilized the Miller compensation scheme tosachieve stability without using external off-chip capacitors. Besides, the circuit uses asdifferentiator to improve the transient response. In [68],...

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...r output voltage within a limited range. However,sthe trade-off among quiescent current (IQ), low-voltage operation, precision and transient responsessimposes critical challenges on the design of LDO =-=[3]-=-.sVarious strategies have been discussed to resolve this problem recently [4-9]. LDO regulatorsswith added current control loops are conceptually simple, have relatively fast transient responses tosbo...

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...cated in a 0.35um CMOS technology. With the excellent transient response and the highest efficiency about 95%, the proposed LDO has the qualification to be integrated in SOC. Keywords: - Transient response, Low Dropout regulator(LDO) , Auxiliary feedback, Miller compensate I. INTRODUCTION Off-chip Capacitor-less LDOs are widely used in cell phone and handheld device [1]. Owing to stability requirement, the conventional LDO usually needs a large output capacitor which is the main obstacle to fully integrating LDOs in SOC designs. To overcome this issue, capacitor-free LDOs have been studied in [2]-[5]. However, because of the limited on-chip size, the internal on-chip output capacitor is smaller and the ESR is increased. This will lead to severe output voltage changes during a fast-load current transient. Since the output capacitor is small, a dominant pole will no longer be located at the output node, unlike the typical LDO. Recently, many researchers have proposed various strategies for improving the transient response performance of the off-chip capacitor-less LDO. Using the capacitor coupling effect for the transient response performance [1– 3] and modifying the driver of the power...

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...e solution. However this technique has only improved transient response but power consumption is not desirable [5]. Several methods are presented to reduce the power consumption of the LDO regulator structure. One of these methods is to use a lowvoltage buffer and a circuit to improve the slew rate [6]. It provides a large dynamic current to charge and discharge capacitor at the gate of pass transistor. In some cases, with current mode buffer, the LDO achieves fast response with small output capacitance, but in these cases, the quiescent current and therefore power dissipation is high [7]. In [8], LDO regulator has used a compensation circuitry to improve stability and reach a desirable transient response. The advantage of this circuit is small output voltage variations. In the contrary it suffers long settling time and high quiescent current. Ebrahim Abiri*, Mohammad Reza Salehi**, and Sara Mohammadalinejadi*** Department of Electrical Engineering, Shiraz university of Technology, Modarres Blvd, Shiraz, Iran, *Abiri@sutech.ac.ir **Salehi@sutech.ac.ir ***S.m.alinejadi@sutech.ac.ir Here to increase the gain-bandwidth product and thus the power efficiency an operational transconductance...

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...r occupies a large chip area, and it is difficult to integrate multiple LDOs on a single chip. In order to design a full on-chip LDO regulator, the number of compensating capacitors must be minimized =-=[3, 6]-=-, and [8]. Figure. 1. Schematic of conventional CMOS LDO Different methods have been introduced recently to improve the performance of full on-chip LDO. The nested Miller compensation (NMC) technique ...

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...hip LDO proposed in [3] gets rid off this problem. But it is not effective at all load currents. The off chip LDO while facilitating SOC design requires deft compensating scheme. Another off chip LDO =-=[7]-=- makes use of a fast path that does both compensation and improving transient response. This forces the design less flexible as it can not be tailor made to suit different requirements of the various ...