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32
Nanometer MOSFET Variation in Minimum Energy Subthreshold Circuits
"... Abstract—Minimum energy operation for digital circuits typically requires scaling the power supply below the device threshold voltage. Advanced technologies offer improved integration, performance, and active-energy efficiency for minimum energy sub-Vt circuits, but are plagued by increased variatio ..."
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Abstract—Minimum energy operation for digital circuits typically requires scaling the power supply below the device threshold voltage. Advanced technologies offer improved integration, performance, and active-energy efficiency for minimum energy sub-Vt circuits, but are plagued by increased variation and reduced ION/IOFF ratios, which degrade the fundamental device characteristics critical to circuit operation by several orders of magnitude. This paper investigates those characteristics and presents design methodologies and circuit topologies to manage their severe degradation. The issues specific to both general logic and dense static random access memories are analyzed, and solutions that address their distinct design metrics are presented. Index Terms—CMOS digital integrated circuits, leakage currents, logic design, low-power electronics, matching, static random access memory (SRAM), subthreshold, yield estimation. I.
Exploring variability and performance in a sub-200 mV processor
- IEEE J. Solid-State Circuits
, 2008
"... Abstract—In this study, we explore the design of a subthreshold processor for use in ultra-low-energy sensor systems. We describe an 8-bit subthreshold processor that has been designed with en-ergy efficiency as the primary constraint. The processor, which is functional below 200 mV, consumes only ..."
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Cited by 16 (0 self)
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Abstract—In this study, we explore the design of a subthreshold processor for use in ultra-low-energy sensor systems. We describe an 8-bit subthreshold processor that has been designed with en-ergy efficiency as the primary constraint. The processor, which is functional below 200 mV, consumes only 3.5 pJ/inst at 350 mV and, under a reverse body bias, draws only 11 nW at 160 mV. Process and temperature variations in sub-threshold circuits can cause dramatic fluctuations in performance and energy consumption and can lead to robustness problems. We investigate the use of body biasing to adapt to process and tem-perature variations. Test-chip measurements show that body bi-asing is particularly effective in subthreshold circuits and can elim-inate performance variations with minimal energy penalties. Re-duced performance is also problematic at low voltages, so we in-vestigate global and local techniques for improving performance while maintaining energy efficiency. Index Terms—Low voltage, process variation, sensor network processing, subthreshold. I.
A Variation-Tolerant Sub-200 mV 6-T Subthreshold SRAM
- IEEE Journal of Solid-State Circuits
, 2008
"... Abstract—In this paper, we present a deep subthreshold 6-T SRAM, which was fabricated in an industrial 0.13 m CMOS technology. We first use detailed simulations to explore the chal-lenges of ultra-low-voltage memory design with a specific emphasis on the implications of variability. We then propose ..."
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Cited by 13 (0 self)
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Abstract—In this paper, we present a deep subthreshold 6-T SRAM, which was fabricated in an industrial 0.13 m CMOS technology. We first use detailed simulations to explore the chal-lenges of ultra-low-voltage memory design with a specific emphasis on the implications of variability. We then propose a single-ended 6-T SRAM design with a gated-feedback write-assist that remains robust deep in the subthreshold regime. Measurements of a test chip show that the proposed memory architecture functions from 1.2 V down to 193 mV and provides a 36 % improvement in energy consumption over the previously proposed multiplexer-based subthreshold SRAM designs while using only half the area. Ad-justable footers and headers are introduced, as well as body bias techniques to extend voltage scaling limits. Index Terms—Low voltage, subthreshold, variation-tolerant SRAM.
Reconfigurable energy efficient near threshold cache architectures
- Microarchitecture, IEEE/ACM International Symposium on
"... Battery life is an important concern for modern embedded processors. Supply voltage scaling techniques can provide an order of magnitude reduction in energy. Current commercial memory technologies have been limited in the degree of supply voltage scaling that can be performed if they are to meet yie ..."
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Cited by 10 (3 self)
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Battery life is an important concern for modern embedded processors. Supply voltage scaling techniques can provide an order of magnitude reduction in energy. Current commercial memory technologies have been limited in the degree of supply voltage scaling that can be performed if they are to meet yield and reliability constraints. This has limited designers from exploring the near threshold operating regions for embedded processors. Summarizing prior work we show how proper sizing of memory cells can guarantee that the memory cell reliability in the near threshold supply voltage region matches that of a standard memory cell. However, this robustness comes with a significant area cost. We show how to employ these cells to build cache architectures that greatly reduce energy consumption. We propose an embedded processor based on these new cache architectures that operates in a low power mode, with minimal impact on full performance runtime. The proposed cache uses near threshold tolerant cache ways to reduce access energy combined with traditional cache ways to maintain performance. The access policy of the cache ways is then dynamically reconfigured to obtain energy efficient performance while minimally impacting the high performance mode runtime. Using near threshold cache architectures we show an energy reduction of 53 % over a traditional filter cache. For the MIBench embedded benchmarks we show on average an 86 % (7.3x) reduction in energy while in low power (10MHz) mode with only an average 2 % increase in runtime in high performance (400MHz) mode. And for SpecInt ap-plications we show a 77 % (4.4x) reduction in energy in low power mode with only an average 4.8 % increase in runtime for high performance mode. In addition we show that these trends hold from 130nm to 45nm technology nodes. 1.
Energy-efficient subthreshold processor design
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, 2009
"... Abstract—Subthreshold circuits have drawn a strong interest in recent ultralow power research. In this paper, we present a highly efficient subthreshold microprocessor targeting sensor application. It is optimized across different design stages including ISA definition, microarchitecture evaluation ..."
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Cited by 9 (1 self)
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Abstract—Subthreshold circuits have drawn a strong interest in recent ultralow power research. In this paper, we present a highly efficient subthreshold microprocessor targeting sensor application. It is optimized across different design stages including ISA definition, microarchitecture evaluation and circuit and implementation optimization. Our investigation concludes that microarchitectural decisions in the subthreshold regime differ significantly from that in conventional superthreshold mode. We propose a new general-purpose sensor processor architecture, which we call the Subliminal Processor. On the circuit side, subthreshold operation is known to exhibit an optimal energy point ( min). However, propagation delay also becomes more sensitive to process variation and can reduce the energy scaling gain. We conduct thorough analysis on how supply voltage and operating frequency impact energy efficiency in a statistical context. With careful library cell selection and robust static RAM design, the Subliminal Processor operates correctly down to 200 mV in a 0.13- m technology, which is sufficiently low to operate at min. Silicon measurements of the Subliminal Processor show a maximum energy efficiency of 2.6 pJ/instruction at 360 mV supply voltage and 833 kHz operating frequency. Finally, we examine the variation in frequency and min across die to verify our analysis of adaptive tuning of the clock frequency and min for optimal energy efficiency. Index Terms—Sensor networks, subthreshold design, min, ultra low power design. I.
Near Threshold Computing: From Single Core to Many-Core Energy Efficient Architectures
, 2011
"... I would like to start by thanking Steve Reinhardt, who in his wisdom took a chance on me as in incoming graduate student. As my advisor for my first several years here his advice was invaluable. When Steve left the University, it was Trevor Mudge who adopted Steve’s students. I am thankful for the a ..."
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Cited by 6 (2 self)
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I would like to start by thanking Steve Reinhardt, who in his wisdom took a chance on me as in incoming graduate student. As my advisor for my first several years here his advice was invaluable. When Steve left the University, it was Trevor Mudge who adopted Steve’s students. I am thankful for the advice he gave me as I switched major research areas and began to focus on what would eventually become my thesis. His career and research advice were important to my development as a student and researcher. In addition I would like to thank Trevor for allowing me the opportunity to build my skill set by including me in countless research proposal writing sessions and allowing me a glimpse behind the curtain of being a faculty member. In addition, I was closely advised by several other faculty members throughout my long career at the University of Michigan. I would like to acknowledge the outside advice from Chaitali Chakrabarti at Arizona State University as well as Krisztian Flautner from ARM for their thoughtful advice. Within the University of Michigan I also received weekly ad-vice from intergroup meetings with David Blaauw, Dennis Sylvester, Thomas Wenisch, and Scott Mahlke. It was these collaborative relationships that yielded such a broad dissertation
Sleep Mode Analysis and Optimization With Minimal-Sized Power Gating Switch for Ultra-Low Vdd Operation
- IEEE Transaction on Very Large Scale Integration (VLSI) Systems 2012, Vol.20, No.4
"... Abstract—This paper investigates the optimization of sleep mode energy consumption for ultra-low CMOS circuits, which is motivated by our findings that minimization of sleep mode energy holds great potential for reducing total energy consumption. We propose a unique approach of using a power gating ..."
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Abstract—This paper investigates the optimization of sleep mode energy consumption for ultra-low CMOS circuits, which is motivated by our findings that minimization of sleep mode energy holds great potential for reducing total energy consumption. We propose a unique approach of using a power gating switch (PGS) in ultra-low regimes. Unlike the conventional manner of using PGSs, our optimization suggests using minimal-sized PGSs with a slightly higher to compensate for voltage drop across the PGS. In SPICE simulations, this reduces total energy consumption by compared to conventional approaches. The effectiveness of the proposed optimization is also confirmed by measurements taken from an ultra-low power microprocessor. Additionally, the feasibility of using minimal PGSs in ultra-low regimes is in-vestigated using SPICE simulations and silicon measurements. Index Terms—MTCMOS, power gating switch, sleeps mode, standby mode, subthreshold operation, ultra-low power.
Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems
"... Abstract—Personal health monitoring systems can offer a costeffective solution for human healthcare. To extend the lifetime of health monitoring systems, we propose a near-threshold ultralow-power multi-core architecture featuring low-power cores, yet capable of executing biomedical applications, wi ..."
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Abstract—Personal health monitoring systems can offer a costeffective solution for human healthcare. To extend the lifetime of health monitoring systems, we propose a near-threshold ultralow-power multi-core architecture featuring low-power cores, yet capable of executing biomedical applications, with multiple instruction and data memories, tightly coupled through flexible crossbar interconnects. This architecture also includes broadcasting mechanisms for the data and instruction memories to optimize system energy consumption by tailoring memory sharing to the target application. Moreover, the architecture enables power gating of the unused memory banks to lower leakage power. Our experimental results show that compared to the state-of-the-art, the proposed architecture achieves 39.5% power savings at high workload requirements (637 MOps/s), and 38.8 % savings at low workload requirements (5 kOps/s), whereby
Misleading energy and performance claims in sub/near threshold digital systems
- In Proc. of Int’l Conf. on Computer Aided Design
"... Abstract — Many of us in the field of ultra-low-Vdd processors expe-rience difficulty in assessing the sub/near threshold circuit techniques proposed by earlier papers. This paper investigates five major pitfalls which are often not appreciated by researchers when claiming that their circuits outper ..."
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Abstract — Many of us in the field of ultra-low-Vdd processors expe-rience difficulty in assessing the sub/near threshold circuit techniques proposed by earlier papers. This paper investigates five major pitfalls which are often not appreciated by researchers when claiming that their circuits outperform others by working at a lower Vdd with a higher energy-efficiency. These pitfalls include: i) overlook the impacts of different technologies and different Vth definitions, ii) only emphasize energy reduction but ignore severe throughput degradation, or expect impractical pipelining depth and parallelism degree to compensate this throughput degradation, iii) unrealistically assume that memory’s Vdd and energy could scale as well as standard cells, iv) use the highest temperature as the worst timing corner as in the super-threshold, but in fact negative temperature becomes much more detrimental in the sub/near threshold regime, v) pursue just-in-need Vdd to compensate effects of PVT, but without considering the high energy loss on DC-DC converters. Therefore, the actual energy benefit from using a sub/near threshold Vdd can be greatly overestimated. This work provides some design guidelines and silicon evidence to ultra-low-Vdd systems. The outlined pitfalls also shed light on future directions in this field. I.
Ultra-Low Energy Digital Controller for Battery-Free Wireless Sensor Network Nodes
, 2011
"... Abstract approved: ..."
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