In this thesis, we present ecient implementation techniques for probabilistic model checking, a method which can be used to analyse probabilistic systems such as randomised distributed algorithms, fault-tolerant processes and communication networks. A probabilistic model checker inputs a probabilistic model and a speci cation, such as \the message will be delivered with probability 1", \the probability of shutdown occurring is at most 0.02" or \the probability of a leader being elected within 5 rounds is at least 0.98", and can automatically verify if the speci cation is true in the model.

This paper describes a new data structure, difference decision diagrams (DDDs), for representing a Boolean logic over inequalities of the form ¡£¢¥¤§¦© ¨ and ¡�¢¥¤���¨ where the variables are integer or real-valued. We give algorithms for manipulating DDDs and for determining functional properties (tautology, satisfiability, and equivalence). DDDs enable an efficient verification of timed systems modeled as, for example, timed automata or timed Petri nets, since both the states and their associated timing information can be represented symbolically, similar to how ROB-DDs represent Boolean predicates.

Feature modeling is used in generative programming and software product-line engineering to capture the common and variable properties of programs within an application domain. The translation of feature models to propositional logics enabled the use of reasoning systems, such as BDD engines, for the analysis and transformation of such models and interactive configurations. Unfortunately, the size of a BDD structure is highly sensitive to the variable ordering used in its construction and an inappropriately chosen ordering may prevent the translation of a feature model into a BDD representation of a tractable size. Finding an optimal order is NP-hard and has for long been addressed by using heuristics. We review existing general heuristics and heuristics from the hardware circuits domain and experimentally show that they are not effective in reducing the size of BDDs produced from feature models. Based on that analysis we introduce two new heuristics for compiling feature models to BDDs. We demonstrate the effectiveness of these heuristics using publicly available and automatically generated models. Our results are directly applicable in construction of feature modeling tools.

We describe BDD-based decision procedures for K. Our approach is inspired by the automata-theoretic approach, but we avoid explicit automata construction. Our algorithms compute the fixpoint of a set of types, which are sets of formulas satisfying some conststency conditions. We use BDDs to represent and manipulate such sets. Experimental results show that our algorithms are competitive with contemporary methods using benchmarks from TANCS 98 and TANCS 2000.

Hierarchical Interface-based Supervisory Control (HISC) is a method to alleviate the state-explosion problem when verifying the controllable and nonblocking properties of a large discrete event system. By decomposing a system as a number of subsystems according to the HISC method, we can verify the subsystems separately and the global system controllability and nonblocking property are guaranteed, so that potentially great computation e#ort is saved. In this thesis, we first present a predicate-based synthesis algorithm for each type of subsystem and then prove the correctness of the algorithms. Then a predicatebased verification algorithm for each type of subsystem is provided. Based on the predicate-based algorithms, a symbolic implementation is proposed by using Binary Decision Diagrams (BDD) and the fact that a subsystem is usually composed of a number of components. With the symbolic implementation, we can handle a much larger subsystem of each type. Two large and complicated examples (with estimated worst-case state space on the order of 10^30 ) extended from the AIP example are provided for demonstrating the capabilities of the algorithms and the implementation. A software tool for the synthesis and verification using our approach is also developed.

Feature cardinalities in feature diagrams determine the num-ber of times a feature and its subtree can be duplicated dur-ing configuration by an operation named “cloning”. Other authors already investigated the problem and pub-lished different proposals of semantics for this construct. However, this previous work is not easily amenable to the formal study of the various properties of feature diagrams and their derived configurations. Also, cross-tree constraint languages still need to be properly extended to account for feature cardinalities. This paper presents an extension of an earlier formal se-mantics of feature diagrams by adding support for feature cardinalities. 1.

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With the vast amount of computing resources distributed throughout the world today, the prospect of e#ectively harnessing these resources has captivated the imaginations of many and motivated both industry and academia to pursue this dream. We believe that fundamental to the realization of this dream is the establishment of trust between application developers and resource donors as donors often receive little or no direct reward for their contributions. The ConCert project (to which this specific undertaking contributes) seeks to develop the theoretical and engineering foundation for grid computing in such a trustless setting based on the notion of certified code.

In this paper, we settle some problems that are encountered when modeling and synthesizing complex industrial systems by the supervisory control theory. First, modeling such huge systems with explicit state-transition models typically results in an intractable model. An alternative modeling approach is to use extended finite automata (EFAs), which is an augmentation of ordinary automata with variables. The main advantage of utilizing EFAs for modeling is that more compact models are obtained. The second problem concerns the ease to understand and implement the supervisor. To handle this problem, we represent the supervisor in a modular manner by extending the original EFAs by compact conditional expressions. This will provide a framework for the users where they can bothmodel their system and obtain the supervisor in form of EFAs. In order to be able to handle complex systems efficiently, the models are symbolically represented by binary decision diagrams (BDDs). All computations that are performed in this framework are based on BDD operations. The framework has been implemented in a supervisory control tool and applied to industrially relevant benchmark problems.

Abstract: Nowadays, more and more computations, in artificial intelligence, knowledge representation, and scientific computations to name a few, require complex data processing and sophisticated algorithms, which are NP hard. Solutions to such problems might range from succinct data representations to parallelized and incremental algorithms. In this paper Catalan related problems are discussed. For efficient computation of Catalan combinations a succinct representation is used and several algorithms are developed. Results show that the suggested approach can be successfully used for solving different Catalan problems. AMS Subject Classification: 68P05