Orthogonal Partitioning and Gated Clock Architecture for Low Power Realization of FSMs [2 citations — 0 self]
Abstract:
In this paper, we address the issue of low power realization of FSMs using decomposition and a gated clock architecture. We decompose an N state machine into two interacting machines with N, N2 states such that N _ x N2. Our objective function is the number of self-edges, which is to be maximized. For all the self-edge conditions, the inputs and clock of the respective machine are disabled to reduce the switching activity and thereby the power. We describe the greedy algorithm which maximizes the objective function. We are attempting to prevent area increase by keeping the number of flip-flops as small as possible. We compared the results of our algorithm with JEDI [7]. In one case, we could achieve power reduction up to 67 % with less area as well. Based on the results, we conclude that our approach is suitable for machines with a large number of states but with relatively small number of outputs.
Citations
| 22 | Synthesis of Multiple Level Logic from Symbolic High-Level Description Languages – Lin, Newton |
| 20 | SIS: A System for Sequential Circuit Synthesis – al - 1992 |
| 13 | Low power realization of finite state machines - a decomposition approach – Chow, Ho, et al. - 1996 |
| 13 | Finite State Machine Decomposition for Low Power – Monteiro, Oliveira - 1998 |
| 3 | Finite State Machine partitioning for low power – Benini, Michelli, et al. - 1998 |
| 3 | State assignment of finite state machine s for low power applications – Wang, Horng - 1996 |
| 1 | State assignment for Low Power – Benini, Michelli - 1995 |
| 1 | Decomposition of Finite State Machines for Area, Delay Minimization – Shelar, Desai, et al. |
