AT&T Laboratories Cambridge
Abstract:
In previous work we have outlined the design of a functional language, SAFL, and argued that it is well suited to hardware description and synthesis. Unlike conventional high-level synthesis languages, SAFL specications capture explicitly resource allocation, variable binding and scheduling. This paper is concerned with the details of the FLaSH compiler: an optimising silicon compiler which translates SAFL specications to RTL Verilog suitable for simulation or synthesis. We describe a number of high-level optimisation and analysis techniques which nd novel application in the eld of hardware-synthesis. In particular, we believe our approach to compiling function denitions into shared resources could be applied advantageously in existing industrial silicon compilers. 1
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