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Table 1: Cases for the worst-case delay

in S²GPS: Slow-Start Generalized Processor Sharing
by Anastasios Stamoulis, Jörg Liebeherr 1996
"... In PAGE 11: ...From #2811#29 wehave that the service rate r k #28t#29 is time dependent. Hence, in order to use #2814#29, wehave to examine the three cases described in Table1 . For ease of notation, in the following we will drop the index k.... ..."
Cited by 7

TABLE V: WORST-CASE DELAY

in TranGen: A SAT-Based ATPG for Path-Oriented Transition Faults
by unknown authors

Table 1. Worst-case delay versus request

in A Memory-Balanced Linear Pipeline Architecture for Trie-based IP Lookup
by unknown authors
"... In PAGE 3: ... Since the oldest request is followed by the most number of requests colliding with the new re- quest, the delay for the new request to wait for entering the pipeline is maximized. Table1 shows the average delay and the maximum delay for the worst cases. The burst length2 of requests varies from 1 to 40.... In PAGE 3: ... The burst length2 of requests varies from 1 to 40. According to Table1 , the worst-case maximum request delay is 94 clock cycles. Con- sidering that the minimum delay for a request is 20, we can conclude that, the delay for passing CAMP varies from 20 to 94 clock cycles under a traffic of 0.... ..."

Table 9: Worst-case delays with all combinations of input offsets.

in Interconnect Tuning Strategies for High-Performance ICs
by Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahul Sharma 1998
Cited by 25

Table 9: Worst-case delays with all combinations of input offsets.

in Interconnect Tuning Strategies for High-Performance ICs
by Andrew Kahng Sudhakar, Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahul Sharma 1998
Cited by 25

Table 2: Voltage configurations for worst-case delay

in Timing Analysis in Presence of Power Supply and Ground Voltage Variation
by Rubil Ahmadi, Farid N. Najm 2003
Cited by 7

Table 2: Voltage configurations for worst-case delay

in Timing analysis in presence of power supply and ground voltage variations
by Rubil Ahmadi 2003
Cited by 7

Table 2: Voltage configurations for worst-case delay

in Timing analysis in presence of power supply and ground voltage variations
by Rubil Ahmadi 2003
Cited by 7

Table 4.4: Worst-case critical path delay.

in Verification and Configuration of a Run-Time Reconfigurable Custom Computing Integrated Circuit for DSP Applications
by A. Lynn Abbott, Joseph G. Tront, Mark F. Cherbaka, Mark F. Cherbaka 1996
Cited by 2

Table 2: Pruned worst-case vectors for circuit of Figure 2

in Algorithms for MIS Vector Generation and Pruning ABSTRACT
by Kenneth S. Stevens
"... In PAGE 6: ... In such cases the pruning algorithm has determined there are no MIS vectors that will delay the output because there are no transistors in series. The complete set of vectors for the falling output for the example gate of Figure 2 are shown in Table2 . This gate (a + bc) is in row 5 of Table 1.... ..."
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