We present a single chip circuit solution to a concept called Near-Sensor Image Processing, which includes image sensing, image processing and feature extraction. We give solutions to the three main implementation problems. A small photodiode read-out unit, which is locally compensated for process variations, a low power processor element and an instruction line driver, suitable for massively parallel processors are described. A 16 16 elements prototype has been built. However most of the results come from simulations of an improved 128 128 matrix. B. Readout unit The photo-current is integrated in a capacitor and converted to a binary value by a comparator (Fig. 3.). The analog readout unit is unique for every SPE. However the performance has to be uniform throughout the SPE-matrix. The differences in component characteristics between different parts of the matrix will result in offset error. This result in fixed pattern noise (FPN). This is not only a problem in large circuits. ...

This paper presents methods for the efficient realization of prototype filters for modulated filter banks. The implementation is based on the lattice structure of the polyphase filters. The lattice coefficients, representing rotations, are approximated by a small number of simple µ-rotations each

Abstract—In this paper, we have proposed a novel blind watermarking architecture towards its hardware implementation in VLSI. In order to facilitate this hardware realization, cellular automata (CA) concept is introduced. The CA has been already accepted as an attractive structure for VLSI

and programmable. It contains no explicit multipliers, adders, or other fixed arithmetic operations; these are implemented using fine-grain interactions of logical particles which are injected into the medium of the cellular automaton, and which represent both data and processors. We sketch a VLSI implementation

Abstract—In this paper, we have proposed a novel blind watermarking architecture towards its hardware implementation in VLSI. In order to facilitate this hardware realization, cellular automata (CA) concept is introduced. The CA has been already accepted as an attractive structure for VLSI

scales. In this paper we suggest a new definition of scale-space, and introduce a class of algorithms that realize it using a diffusion process. The diffusion coefficient is chosen to vary spatially in such a way as to encourage intraregion smoothing in preference to interregion smoothing. It is shown

Abstract. This paper presents the hardware realization of a Hamming artificial neural network, and demonstrates its use in a high-speed precision alignment system. High degree of parallelism is exploited in the proposed architecture, where the result of NxN array of sum of products is provided

In this paper, we present a novel high-speed dual-core programmable decoder architecture for LDPC convolutional codes and their tail-biting versions. This architecture uses a modified Min-Sum algorithm and enables the decoding of a multitude of codes with different node degree distributions, rates and block lengths. We show how the parallelization concepts are derived using the properties of the bipartite graphs underlying the codes. Moreover, the hardware elements composing the architecture will be presented and analyzed in detail. The programmability of the decoder is also considered. Finally, we present the synthesis results for a prototype ASIC which is capable of achieving high decoding throughput still with very high flexibility, relatively low power consumption and small area.

Abstract—In this paper, we have proposed a novel blind watermarking architecture towards its hardware implementation in VLSI. In order to facilitate this hardware realization, cellular automata (CA) concept is introduced. The CA has been already accepted as an attractive structure for VLSI

The coefficient values and number representations of digital FIR filters have significant impacts on the complexity of their VLSI realizations and thus on the system cost and performance. So, making a good tradeoff between implementation costs and quantization errors is essential for designing