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Combinatorial Optimization in VLSI design
- Combinatorial Optimization: Methods and Applications. IOS
"... Abstract VLSI design is probably the most fascinating application area of combinatorial optimization. Virtually all classical combinatorial optimization problems, and many new ones, occur naturally as subtasks. Due to the rapid technological development and major theoretical advances the mathematics ..."
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Abstract VLSI design is probably the most fascinating application area of combinatorial optimization. Virtually all classical combinatorial optimization problems, and many new ones, occur naturally as subtasks. Due to the rapid technological development and major theoretical advances
Technical Visualizations in VLSI Design
, 2001
"... Visualization techniques were applied to several different types of VLSI design and simulation data. A number of different visualizations have been tried, with varying results. Examples include 3D visualization of voltage and currents from fullwave interconnect analysis, on-chip clock distribution n ..."
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Visualization techniques were applied to several different types of VLSI design and simulation data. A number of different visualizations have been tried, with varying results. Examples include 3D visualization of voltage and currents from fullwave interconnect analysis, on-chip clock distribution
The Design of VLSI Design Methods
"... The Mead-Conway VLSI design and implementation methodologies were deliberately generated to be simple and accessible, and yet have wide coverage and efficiency in application. An overview is given of the methods used to "design the design methodology. " We sketch the results and the status ..."
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The Mead-Conway VLSI design and implementation methodologies were deliberately generated to be simple and accessible, and yet have wide coverage and efficiency in application. An overview is given of the methods used to "design the design methodology. " We sketch the results
Technical Visualizations in VLSI Design
"... Visualization techniques were applied to several different types of VLSI design and simulation data. A number of different visualizations have been tried, with varying results. Examples include 3D visualization of voltage and currents from fullwave interconnect analysis, on-chip clock distribution n ..."
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Visualization techniques were applied to several different types of VLSI design and simulation data. A number of different visualizations have been tried, with varying results. Examples include 3D visualization of voltage and currents from fullwave interconnect analysis, on-chip clock distribution
Algorithm Engineering and VLSI Design
, 1993
"... The task of producing a VLSI architecture that will solve a given problem contains many design decisions. The effects of these decisions on the final design are often difficult to quantify. We will compare three different implementations of a systolic architecture for solving the knapsack problem ..."
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The task of producing a VLSI architecture that will solve a given problem contains many design decisions. The effects of these decisions on the final design are often difficult to quantify. We will compare three different implementations of a systolic architecture for solving the knapsack problem
The Hierarchical Analysis of VLSI Designs
, 1982
"... The views and conclusions conlaincd in this document arc those of the author and should not be interprelcd as representing the official policics, either expressed or ilnplied, of Ihc l)cfcnse Advanced Rcscarch Projects Agency or the US govermncnt. This document was 'mbmitted in parlial fulfillm ..."
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fulfillment of lhe requirements for the degree of I)octor of Philosophy. As the complexity of integrated circuit designs increases, tile task of verifying that the masks are correct becomes very time consuming. Fortunately, tile wide acceptance of hierarchical mask description fornaats allows tile development
VLSI Design Group
"... In this paper fast locking CMOS phase locked loop is proposed. It is designed using Cadence virtuoso gpdk 45nm CMOS technology. It is used 1 volt power supply for operation of the circuit. This proposed circuit will be very useful in clock generation in microprocessor, frequency synthesizer for cell ..."
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In this paper fast locking CMOS phase locked loop is proposed. It is designed using Cadence virtuoso gpdk 45nm CMOS technology. It is used 1 volt power supply for operation of the circuit. This proposed circuit will be very useful in clock generation in microprocessor, frequency synthesizer
Micro Electronics and VLSI design,
"... Operational Tran conductance Amplifier (OTA). The 0.18μm CMOS process is used for Design and Simulation of this OTA. This OTA having a bias voltage 1.8 with supply voltage 1.8 V. The design and Simulation of this OTA is done using CADENCE Spectere environment with UMC 0.18μm technology file. The Sim ..."
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Operational Tran conductance Amplifier (OTA). The 0.18μm CMOS process is used for Design and Simulation of this OTA. This OTA having a bias voltage 1.8 with supply voltage 1.8 V. The design and Simulation of this OTA is done using CADENCE Spectere environment with UMC 0.18μm technology file
Results 1 - 10
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4,804