• Documents
  • Authors
  • Tables
  • Log in
  • Sign up
  • MetaCart
  • DMCA
  • Donate

CiteSeerX logo

Advanced Search Include Citations

Tools

Sorted by:
Try your query at:
Semantic Scholar Scholar Academic
Google Bing DBLP
Results 1 - 10 of 167
Next 10 →

Software pipelining: An effective scheduling technique for VLIW machines

by Monica Lam , 1988
"... This paper shows that software pipelining is an effective and viable scheduling technique for VLIW processors. In software pipelining, iterations of a loop in the source program are continuously initiated at constant intervals, before the preceding iterations complete. The advantage of software pipe ..."
Abstract - Cited by 581 (3 self) - Add to MetaCart
This paper shows that software pipelining is an effective and viable scheduling technique for VLIW processors. In software pipelining, iterations of a loop in the source program are continuously initiated at constant intervals, before the preceding iterations complete. The advantage of software

Value Prediction in VLIW Machines

by Tarun Nakra Rajiv, Rajiv Gupta, Mary Lou Soffa - In Proc. of the 26th Annual International Symposium on Computer Architecture, ACM , 1999
"... The performance of VLIW architectures is dependent on the capability of the compiler to detect and exploit instruction-level parallelism during instruction scheduling. To exploit the detected parallelism, instructions are reordered to reduce the length of the code schedule and minimize the cycle cou ..."
Abstract - Add to MetaCart
consists of two execution engines, one for executing the original VLIW code, and the other for executing compensation code after a misprediction. Any code executed due to mispredictions is executed in parallel with the VLIW instructions. The instruction set and hardware of a traditional VLIW machine

Value Prediction in VLIW Machines

by Tarun Nakra, Rajiv Gupta, Mary Lou Soffa , 1999
"... ..."
Abstract - Cited by 11 (2 self) - Add to MetaCart
Abstract not found

Scheduling Load Operations on VLIW Machines

by Charles R. Hardnett, Krishna V. Palem, Rodric M. Rabbah
"... There continues to be a widening gap between processor speeds and memory access time. This gap is seen in systems ranging from embedded computing systems to high-performance supercomputing systems. In this paper, we present an instruction scheduling algorithm that can be targetted towards VLIW archi ..."
Abstract - Add to MetaCart
There continues to be a widening gap between processor speeds and memory access time. This gap is seen in systems ranging from embedded computing systems to high-performance supercomputing systems. In this paper, we present an instruction scheduling algorithm that can be targetted towards VLIW

Using Sacks to Organize Registers in VLIW Machines

by Josep Llosa, Mateo Valero, Jose A.B. Fortes, Eduard Ayguade - Proceedings of the Third joint International Conference on Vector and Parallel Processing, CONPAR'94-VAPP VI, volume 854 of LNCS , 1994
"... . This paper analyses the register requirements of software pipelined inner loops. When the number of functional units and/or the number of stages of individual functional units is increased, the number of registers required may be prohibitive in chip area and cycle time. We characterize lifetime of ..."
Abstract - Cited by 3 (0 self) - Add to MetaCart
. This paper analyses the register requirements of software pipelined inner loops. When the number of functional units and/or the number of stages of individual functional units is increased, the number of registers required may be prohibitive in chip area and cycle time. We characterize lifetime of values in pipelined loops with their loop register locality (LRL). Based on this characteristic, we propose a new organization of the register file in order not to affect cycle time and also reduce area, while increasing the number of registers. This can be useful to minimize the frequency of spill at a reasonable cost. The spill code can increase the minimum initiation interval and decrease loop performance. This new organization consists of a small high bandwidth multiported register file and a low bandwidth port-limited register file called sack. A mechanism to assign values to the sack is presented. We demonstrate the effectiveness of our approach by experimenting with a collection of ...

Simultaneous Multithreading VLIW Processor Architecture

by Victor M. Goulart Ferreira, Hiroto Yasuura
"... This paper introduces the concept of a novel archi-tecture, SMTVLIW: Simultaneous Multithreading VLIW Machine, which incorporates real-time task scheduling at the microarchitecture level of VLIW-like processors. This architecture permits to simultaneously run an arbitrary number of threads, building ..."
Abstract - Add to MetaCart
This paper introduces the concept of a novel archi-tecture, SMTVLIW: Simultaneous Multithreading VLIW Machine, which incorporates real-time task scheduling at the microarchitecture level of VLIW-like processors. This architecture permits to simultaneously run an arbitrary number of threads

Partitioned Schedules for Clustered VLIW Architectures

by Marcio Merino Fernandes - In Proc., 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP'1998 , 1998
"... This paper presents results on a new approach to partitioning a modulo-scheduled loop for distributed execution on parallel clusters of functional units organized as a VLIW machine. A distinctive characteristic of this architecture is the use of register files organized by means of queues, which res ..."
Abstract - Cited by 11 (4 self) - Add to MetaCart
This paper presents results on a new approach to partitioning a modulo-scheduled loop for distributed execution on parallel clusters of functional units organized as a VLIW machine. A distinctive characteristic of this architecture is the use of register files organized by means of queues, which

DAISY: Dynamic Compilation for 100% Architectural Compatibility

by Kemal Ebcioglu, Erik R. Altman , 1997
"... Although VLIW architectures offer the advantages of simplicity of design and high issue rates, a major impediment to their use is that they are not compatible with the existing software base. We describe new simple hardware features for a VLIW machine we call DAISY (Dynamically Architected Instructi ..."
Abstract - Cited by 206 (13 self) - Add to MetaCart
Although VLIW architectures offer the advantages of simplicity of design and high issue rates, a major impediment to their use is that they are not compatible with the existing software base. We describe new simple hardware features for a VLIW machine we call DAISY (Dynamically Architected

Code Positioning for VLIW Architectures

by Andrea Cilio And, Henk Corporaal
"... Several studies have considered reducing instruction cache misses and branch penalty stall cycles by means of various forms of code placement. Most proposed approaches rearrange procedures or basic blocks in order to speed up execution on sequential architectures with branch prediction. Moreover, ..."
Abstract - Add to MetaCart
, most works focus mainly on instruction cache performance and disregard execution cycles. To the best of our knowledge, no work has specifically addressed statically scheduled ILP machines like VLIWs, with control-transfer delay slots.

From Machine Scheduling to VLIW Instruction Scheduling

by Benot Dupont De Dinechin
"... ... and instruction scheduling problems on modern VLIW processors such as the STMicroelectronics ST200. Our motivations are to apply the machine scheduling techniques that are relevant to instruction scheduling in VLIW compilers, and to understand how processor micro-architecture features impact ..."
Abstract - Cited by 3 (0 self) - Add to MetaCart
... and instruction scheduling problems on modern VLIW processors such as the STMicroelectronics ST200. Our motivations are to apply the machine scheduling techniques that are relevant to instruction scheduling in VLIW compilers, and to understand how processor micro-architecture features impact
Next 10 →
Results 1 - 10 of 167
Powered by: Apache Solr
  • About CiteSeerX
  • Submit and Index Documents
  • Privacy Policy
  • Help
  • Data
  • Source
  • Contact Us

Developed at and hosted by The College of Information Sciences and Technology

© 2007-2019 The Pennsylvania State University