-in architecture; a presentation of a new PCI-based FPGA accelerator system suited for image processing style applications; and theoretical calculations and empirical measurements of the system that was actually built. 1 Introduction The design, implementation and performance analysis of a FPGA-based co

We consider packing in the commercial FPGA context and examine the speed, performance and power trade-offs associated with packing in a state-of-the art FPGA – the Xilinx R○ Virtex TM-5 FPGA. Two aspects of packing are discussed: 1) packing for general logic blocks, and 2) packing for large IP

This paper describes the new version of SCCircal, a static compiler for XCircal targeted to Xilinx Virtex architecture. This compiler, written in Java, is now capable of providing a real FPGA implementation for almost any Circal process specification. Thus it supports hierarchy, abstraction

not be available in some architectures. Review the MPMC architecture-specific features in the following table for more information.

Abstract. We use the Xilinx Virtex II Pro ™ technology as prototyping platform to design a MOLEN polymorphic processor, a custom computing machine based on the co-processor architectural paradigm. The PowerPC embedded in the FPGA is operating as a general purpose (core) processor

-efficiency, with minimal performance degradation. We then describe packing techniques for large IP blocks, namely, block RAMs and DSPs. We pack circuits into the large blocks in a way that leverages the unique block RAM and DSP layout/architecture in Virtex-5, achieving significantly improved design performance.

ABSTRACT This paper analyzes the dynamic power consumption in the fabric of Field Programmable Gate Arrays (FPGAs) by taking advantage of both simulation and measurement. Our target device is Xilinx Virtex™-II family, which contains the most recent and largest programmable fabric. We identify

. This paper presents a new version of the MUXTREE embryonic cell suitable for implementation in a commercial Virtex FPGA from Xilinx^TM. The main characteristic of the new cell is the structure of its memory. It is demonstrated that by implementing the memory as a look-up table, it is possible

SRAM based logic devices such as FPGAs have some susceptibility to SEU and functional interruption. This paper describes several reliable mitigation techniques for the Virtex series FPGA architecture, which will retain functional integrity while static upsets are detected and corrected

This application note describes the different local clocking resources available in the Virtex™-II architecture. Along with a reference design, this application note details how to use the local clocking resources in source-synchronous applications.