this article is one which doesn't directly touch on the field of computer software at all, but which comes from the field of medicine. Before modern medicine existed, illness and disease were believed to be the fault of evil spirits, angry gods, demons, and all manner of other causes. If it were possible to find some magic cure which would keep the demons at bay then a great many medical problems could be solved. Scientific research into the real reasons for illness and disease destroyed these hopes of magical cures. There is no single, universal cure since there's no single problem, and each new problem (or even variation of an existing problem) needs to be addressed via a problem-specific solution

On transferring VDM verification techniques to Z

at design time, before system implementation. Traditional verification methods involving system testing are not sufficient or are not possible, given time constraints, for verification or validation of reconfigurable systems. This report examines state-of-the-art verification techniques and individual

show techniques for demonstrating confluence of complex processes in a compositional manner and we study properties of conflu-ent systems that can prove useful for their verification. These results give rise to a methodology for system verification which we illustrate by proving the correctness of two

There has been a significant amount of recent research in low-cost mechanisms for detecting errors in computer execution that are due to hardware faults. One exciting, low-cost approach to error detec-tion is dynamic verification (sometimes also called online testing or runtime invariant checking

We report on the results of a project which applied LOTOS to safety-critical case studies, determined the veri cation needs of real life applications, and developed tools for ASN.1 to LOTOS translation and equational reasoning.

The validation of hardware, software, and firmware of a System-On-a-Chip (SoC) design can be accomplished using 90-nm FPGA-based prototypes. FPGA prototypes make it possible for SoC designs to be delivered on time, on budget, and on market target. For successful design testing with prototypes, tools need to provide automation while maintaining flexibility. This paper focuses on what's required in an RTL–to–PCB compilation and debugging flow that targets multiple state-of-the-art 90-nm FPGAs. Requirements such as hardware/software trade-off testing, design checking, multi-FPGA partitioning, design debug, incremental compilation, pin planning, design security and tool automation will be discussed. In this paper, we’ll present the benefits of ASIC and SoC prototyping in 90-nm-FPGAs. We’ll describe the SoC development process and its challenges and requirements for FPGA-based prototyping. We’ll present specific solutions outlining their scope, benefit and limitations. We’ll then conclude with how the risks of ASIC or SoC development can be reduced even further using structured ASICs.

Psychometric validation of the

This paper presents and compares three techniques for mechanized verification of state-oriented design descriptions. The goal of this work is to gain insight into quantitative aspects of different modular verification techniques. One of the three verification techniques presented here is a

Abstract. Combining verification methods developed separately for software and hardware is motivated by the industry’s need for a technology that would make formal verification of realistic software/hardware co-designs practical. We focus on techniques that have proved successful in each of the two