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Underflow Revisited
, 1999
"... Underflow is a floatingpoint phenomenon. Although the use of gradual underflow as defended in [2] and [5] is now widespread, most numerical analysts may not be aware of the fact that several implementations of the same principle are in existence, leading to different behaviour of code on different ..."
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of the phenomenon and not on any implementation issues. Many programmers are also unaware of the fact that the IEEE 754 and 854 standards do not guarantee that a program will deliver identical results on all conforming systems. Of all the differences that can occur crossplatform, the underflow exception is just
Buffer Minimization in EarliestDeadline First Scheduling of Dataflow Graphs
"... Symbolic schedulability analysis of dataflow graphs is the process of synthesizing the timing parameters (i.e. periods, phases, and deadlines) of actors so that the task system is schedulable and achieves a high throughput when using a specific scheduling policy. Furthermore, the resulted schedule m ..."
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) The construction of an abstract affine schedule of the graph that excludes overflow and underflow exceptions and minimizes the buffering requirements assuming some precedences between jobs. (2) Symbolic deadlines adjustment that guarantees precedences without the need for lockbased synchronizations. (3
Affine dataflow graphs for the synthesis of hard realtime applications
 In Proceedings of the 12th International Conference on Application of Concurrency to System Design
, 2012
"... Abstract—Dataflow models ease the task of constructing feasible schedules of computations and communications of highassurance embedded applications. One key and open issue is how to schedule dataflow graphs so as to minimize the buffering of data and reduce endtoend latency. Most of the propose ..."
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that minimizes buffering requirements and, in addition, guarantees the absence of overflow and underflow exceptions over communication channels. (3) Depending on the chosen scheduling policy (earliestdeadline first or ratemonotonic), we concretize the symbolic schedule by defining the period and the phase
unknown title
"... Although there have been misconceptions about it, gradual underflowfits naturally into theproposedstandard and leads to simple, generalstatements about the arithmetic. Underflowand theDenormalizedNumbers L the spring of 1980, after meeting regularly for over two years, a subcommittee of the IEEE Com ..."
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, their encoding in storage, and the specification of operations upon them. To this foundation may be added features that cope with exceptions such as over/underflow. The proposed standard was developed this way, designed to be a complete scheme for arithmetic, balancedbetween utility and implementation cost
Exact Geometric Predicates using Cascaded Computation
 In Proc. 14th Annu. ACM Sympos. Comput. Geom
, 1998
"... In this paper we talk about a new efficient numerical approach to deal with inaccuracy when implementing geometric algorithms. Using various floatingpoint filters together with arbitrary precision packages, we develop an easytouse expression compiler called EXPCOMP. EXPCOMP supports all common op ..."
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operations +; \Gamma; \Delta; =; p . Applying a new semistatic filter, EXPCOMP combines the speed of static filters with the power of dynamic filters. The filter stages deal with all kinds of floatingpoint exceptions, including underflow. The resulting programs show a very good runtime behaviour. 1
Complete Interval Arithmetic and its Implementation on the Computer
"... Abstract: Let IIR be the set of closed and bounded intervals of real numbers. Arithmetic in IIR can be defined via the power set IPIR of real numbers. If divisors containing zero are excluded, arithmetic in IIR is an algebraically closed subset of the arithmetic in IPIR, i.e., an operation in IIR pe ..."
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that arithmetic operations can be extended to all elements of the set (IIR). Let F ⊂ IR denote the set of floatingpoint numbers. On the computer, arithmetic in (IIR) is approximated by arithmetic in the subset (IF) of closed intervals with floatingpoint bounds. The usual exceptions of floatingpoint arithmetic
An IEEE 7542008 decimal parallel and pipelined FPGA floatingpoint multiplier
 in Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL ’10
, 2010
"... Abstract—Decimal floating point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, scientific, commercial, and financial applications. In this paper we present an IEEE 7542008 compliant parallel decimal floatingp ..."
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rounding modes, exception handling, overflow, and gradual underflow. Several pipeline stages can be added to increase throughput. Furthermore, different modifications are analyzed including shifting by means of hardwired multipliers and delayed carry propagation adders. I.
ErrorBounding in LevelIndex Computer Arithmetic
 in Numerical Methods and Error
, 1966
"... . This paper proposes the use of levelindex (LI) and symmetric levelindex (SLI) computer arithmetic for practical computation with error bounds. Comparisons are made with floatingpoint and several advantages are identified. 1 Introduction Any approach to the general problem of assessing the tot ..."
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and circuitry that carry out floatingpoint arithmetic. One goal of this effort has been to minimize rounding errors. Another was to ensure that exceptional conditions, such as underflow and overflow, are detected and reported because their occurrence can completely invalidate the results of a computation
D76128 KarlsruheComplete Interval Arithmetic and its Implementation on the Computer
"... Abstract: Let IIR be the set of closed and bounded intervals of real numbers. Arithmetic in IIR can be defined via the power set IPIR (the set of all subsets) of real numbers. If divisors containing zero are excluded, arithmetic in IIR is an algebraically closed subset of the arithmetic in IPIR, i.e ..."
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). The paper shows that arithmetic operations can be extended to all elements of the set (IIR). On the computer, arithmetic in (IIR) is approximated by arithmetic in the subset (IF) of closed intervals over the floatingpoint numbers F ⊂ IR. The usual exceptions of floatingpoint arithmetic like underflow
An FPGA Based High Performance IEEE 754 Digit Recurrence Floating Point Double Precision Divisor Using Verilog
"... Current Floatingpoint divisor architectures have low frequency, larger area and high latency in nature. With advent of more graphic, scientific and medical applications, floating point dividers have become indispensable and increasingly important. However, most of these modern applications need hig ..."
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the overall latency of the divisor is reduced to 30 clock cycles, i.e. 52 % less compared to conventional divisors. This design is mapped onto a Virtex6 FPGA and an operating frequency of 452.69 MHz is achieved. The proposed design also handles all the IEEE specified four rounding modes, overflow, underflow
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