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136,518
TwoBit Gates Are Universal for Quantum Computation
, 1995
"... A proof is given, which relies on the commutator algebra of the unitary Lie groups, that quantum gates operating on just two bits at a time are sufficient to construct a general quantum circuit. The best previous result had shown the universality of threebit gates, by analogy to the universality of ..."
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Cited by 182 (10 self)
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of the Toffoli threebit gate of classical reversible computing. Twobit quantum gates may be implemented by magnetic resonance operations applied to a pair of electronic or nuclear spins. A "gearbox quantum computer" proposed here, based on the principles of atomic force microscopy, would permit
twogat05.latex–submitted to Phys. Rev. A (AT5101); condmat/9407022 Twobit gates are universal for quantum computation
, 1994
"... A proof is given, which relies on the commutator algebra of the unitary Lie groups, that quantum gates operating on just two bits at a time are sufficient to construct a general quantum circuit. The best previous result had shown the universality of threebit gates, by analogy to the universality of ..."
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of the Toffoli threebit gate of classical reversible computing. Twobit quantum gates may be implemented by magnetic resonance operations applied to a pair of electronic or nuclear spins. A “gearbox quantum computer ” proposed here, based on the principles of atomic force microscopy, would permit the operation
Elementary Gates for Quantum Computation
, 1995
"... We show that a set of gates that consists of all onebit quantum gates (U(2)) and the twobit exclusiveor gate (that maps Boolean values (x,y) to (x,x⊕y)) is universal in the sense that all unitary operations on arbitrarily many bits n (U(2 n)) can be expressed as compositions of these gates. We in ..."
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Cited by 276 (11 self)
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constructions of quantum computational networks. We derive upper and lower bounds on the exact number of elementary gates required to build up a variety of two and threebit quantum gates, the asymptotic number required for nbit DeutschToffoli gates, and make some observations about the number required
Simulating Physics with Computers
 SIAM Journal on Computing
, 1982
"... A digital computer is generally believed to be an efficient universal computing device; that is, it is believed able to simulate any physical computing device with an increase in computation time of at most a polynomial factor. This may not be true when quantum mechanics is taken into consideration. ..."
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Cited by 601 (1 self)
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A digital computer is generally believed to be an efficient universal computing device; that is, it is believed able to simulate any physical computing device with an increase in computation time of at most a polynomial factor. This may not be true when quantum mechanics is taken into consideration. This paper considers factoring integers and finding discrete logarithms, two problems which are generally thought to be hard on a classical computer and have been used as the basis of several proposed cryptosystems. Efficient randomized algorithms are given for these two problems on a hypothetical quantum computer. These algorithms take a number of steps polynomial in the input size, e.g., the number of digits of the integer to be factored. AMS subject classifications: 82P10, 11Y05, 68Q10. 1 Introduction One of the first results in the mathematics of computation, which underlies the subsequent development of much of theoretical computer science, was the distinction between computable and ...
SIS: A System for Sequential Circuit Synthesis
, 1992
"... SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logiclevel description of a sequential circuit, it produces an optimized netlist in the target technology while preserving the sequential inputoutput b ..."
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Cited by 514 (41 self)
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, new logic optimization and verification algorithms, ASTG (asynchronous signal transition graph) manipulation, and synthesis for PGA’s (programmable gate arrays). The second part contains a tutorial example illustrating the design process using SIS.
A New Kind of Science
, 2002
"... “Somebody says, ‘You know, you people always say that space is continuous. How do you know when you get to a small enough dimension that there really are enough points in between, that it isn’t just a lot of dots separated by little distances? ’ Or they say, ‘You know those quantum mechanical amplit ..."
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Cited by 850 (0 self)
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“Somebody says, ‘You know, you people always say that space is continuous. How do you know when you get to a small enough dimension that there really are enough points in between, that it isn’t just a lot of dots separated by little distances? ’ Or they say, ‘You know those quantum mechanical amplitudes you told me about, they’re so complicated and absurd, what makes you think those are right? Maybe they aren’t right. ’ Such remarks are obvious and are perfectly clear to anybody who is working on this problem. It does not do any good to point this out.” —Richard Feynman [1, p.161]
Monotone Complexity
, 1990
"... We give a general complexity classification scheme for monotone computation, including monotone spacebounded and Turing machine models not previously considered. We propose monotone complexity classes including mAC i , mNC i , mLOGCFL, mBWBP , mL, mNL, mP , mBPP and mNP . We define a simple ..."
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Cited by 2837 (11 self)
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We give a general complexity classification scheme for monotone computation, including monotone spacebounded and Turing machine models not previously considered. We propose monotone complexity classes including mAC i , mNC i , mLOGCFL, mBWBP , mL, mNL, mP , mBPP and mNP . We define a simple notion of monotone reducibility and exhibit complete problems. This provides a framework for stating existing results and asking new questions. We show that mNL (monotone nondeterministic logspace) is not closed under complementation, in contrast to Immerman's and Szelepcs 'enyi's nonmonotone result [Imm88, Sze87] that NL = coNL; this is a simple extension of the monotone circuit depth lower bound of Karchmer and Wigderson [KW90] for stconnectivity. We also consider mBWBP (monotone bounded width branching programs) and study the question of whether mBWBP is properly contained in mNC 1 , motivated by Barrington's result [Bar89] that BWBP = NC 1 . Although we cannot answer t...
Route Packets, Not Wires: OnChip Interconnection Networks
, 2001
"... Using onchip interconnection networks in place of adhoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules (processors, memories, peripherals, etc...) communicate by sending packets to one another over the network. The structur ..."
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Cited by 864 (10 self)
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Using onchip interconnection networks in place of adhoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules (processors, memories, peripherals, etc...) communicate by sending packets to one another over the network. The structured network wiring gives wellcontrolled electrical parameters that eliminate timing iterations and enable the use of highperformance circuits to reduce latency and increase bandwidth. The area overhead required to implement an onchip network is modest, we estimate 6.6%. This paper introduces the concept of onchip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks. 1
The Future of Wires
, 1999
"... this paper we first discuss the wire metrics of interest and examine them in a contemporary 0.25m process. We then discuss technology scaling over the next several generations, from SIA and other predictions, and how our wire metrics trend over that time. We will examine the delay and bandwidth lim ..."
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Cited by 508 (7 self)
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this paper we first discuss the wire metrics of interest and examine them in a contemporary 0.25m process. We then discuss technology scaling over the next several generations, from SIA and other predictions, and how our wire metrics trend over that time. We will examine the delay and bandwidth limitations of both long global wires and short local wires and discuss architectural design techniques that help us avoid the limitations of scaled wires.
LowPower CMOS Digital Design
 JOURNAL OF SOLIDSTATE CIRCUITS. VOL 27, NO 4. APRIL 1992 413
, 1992
"... Motivated by emerging batteryoperated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for lowpower operation are shown which use the ..."
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Cited by 570 (20 self)
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Motivated by emerging batteryoperated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for lowpower operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturalbased scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption.
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