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Results 11 - 20
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22
Adapting to Dynamic Heterogeneity: . . .
, 2008
"... As the computing industry enters the multicore era, exponential growth in the number of transistors on a chip continues to present challenges and opportunities to computer architects. This dissertation identifies and addresses one emerging issue in particular: that of dynamic heterogeneity, which c ..."
Abstract
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can arise, even among physically homogeneous cores, from changing reliability, power, or thermal conditions, or different cache and TLB contents. This heterogeneity greatly complicates software’s traditional task of assigning computation to cores because the conditions can change more rapidly than
Improved Address-Space Switching on Pentium Processors by Transparently Multiplexing User Address Spaces
- Center for Information Technology, Sankt Augustin
, 1995
"... Address-space switch requires a TLB flush on many processors. With increasing TLB size, the secondary costs of address-space switching due to TLB refill can thus increase substantially. For the Pentium processor, we describe an optimization to avoid TLB flush in many cases. The method is transpa ..."
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Address-space switch requires a TLB flush on many processors. With increasing TLB size, the secondary costs of address-space switching due to TLB refill can thus increase substantially. For the Pentium processor, we describe an optimization to avoid TLB flush in many cases. The method
Context-Aware Address Translation for High Performance SMP Cluster System
"... Abstract—User-level communication allows an application process to access the network interface directly. Bypassing the kernel requires that a user process accesses the network interface using its own virtual address which should be translated to a physical address. A small caching structure which i ..."
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is similar to the hardware TLB on the host processor has been used to cache the mappings between virtual and physical addresses on the network interface memory. In this study, we propose a new TLB architecture for the network interface. The proposed architecture splits an original caching structure
SAMSUNG Tech. Conference Abstract Context Switching and IPC Performance Comparison between uClinux and Linux on the ARM9 based Processor
"... uClinux is a derivation of Linux kernel intended for MMU-less processors. It provides a single shared address space for all processes while the Linux kernel provides a separate virtual address space for each process using hardware MMU (memory management unit). In this paper, we implemented Linux and ..."
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and uClinux kernels on the same ARM9 platform and compared the performance. The ARM9 processor features virtually indexed caches and a TLB without address space tag. Therefore Linux should flush entire cache and TLB on each context switch which is very costly. uClinux, however, contents of caches and a
Full-system analysis and characterization of interactive smartphone applications
- in: Workload Characterization (IISWC’11), 81–90, doi:\bibinfo{doi}{10.1109/ IISWC.2011.6114205
, 2011
"... Abstract-Smartphones have recently overtaken PCs as the primary consumer computing device in terms of annual unit shipments. Given this rapid market growth, it is important that mobile system designers and computer architects analyze the characteristics of the interactive applications users have co ..."
Abstract
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Cited by 27 (3 self)
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come to expect on these platforms. With the introduction of highperformance, low-power, general purpose CPUs in the latest smartphone models, users now expect PC-like performance and a rich user experience, including high-definition audio and video, high-quality multimedia, dynamic web content
unknown title
"... Processor caches are designed to store the most recently used subset of the main memory and to provide this subset with low latency. Most contemporary cache architectures use physically indexed caches to facilitate cache coherency and to avoid cache flushing during a context switch. Memory of multip ..."
Abstract
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with the same working set to follow upon each other to reuse the content of the cache, but in contemporary operating systems the sequence of execution is independent of working-set aspects. Our approach to improve system performance uses information derived from the translation lookaside buffer (TLB) to detect
A methodology for detailed . . .
, 2004
"... In this paper, we revisit the problem of performance prediction on SMP machines, motivated by the need for selecting parallelization strategy for random write reductions. Such reductions frequently arise in data mining algorithms. In our previous work, we have developed a number of techniques for pa ..."
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of these techniques for a given problem, dataset, and machine?”. This paper addresses this question by developing an analytical performance model that captures a two-level cache, coherence cache misses, TLB misses, locking overheads, and contention for memory. Analytical model is combined with results from micro
a:1:.tI PACKARD Pattern-Addressable Memory and the Chameleon Board: A Brief Overview and User's Guide
, 1992
"... database, knowledge-based systems, pattern recognition, parallel architectures, content-addressable memories, ~SI The Chameleon board and its attendant software is designed to provide a hardware and software environment for experimenting with a novel memory system called pattern-addressable memory. ..."
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database, knowledge-based systems, pattern recognition, parallel architectures, content-addressable memories, ~SI The Chameleon board and its attendant software is designed to provide a hardware and software environment for experimenting with a novel memory system called pattern-addressable memory
Linux on the PowerPC: Optimizing Modern Operating Systems for Modern Processors
"... In highly cached and pipelined machines, operating system performance and aggregate user/system performance is enormously sensitive to small changes in cache and TLB hit rates. We have implemented a variety of changes in the memory management of a native port of the Linux operating system to the Pow ..."
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In highly cached and pipelined machines, operating system performance and aggregate user/system performance is enormously sensitive to small changes in cache and TLB hit rates. We have implemented a variety of changes in the memory management of a native port of the Linux operating system
Hardware Monitors for Dynamic Page Migration
"... In this paper, we first introduce a profile-driven online page migration scheme and investigate its impact on the performance of multithreaded applications. We use centralized lightweight, inexpensive plug in hardware monitors to profile the memory access behavior of an application, and then migrate ..."
Abstract
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Cited by 5 (0 self)
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of using cache miss profiles, Translation Lookaside Buffer (TLB) miss profiles and the content of the on-chip TLBs using the valid bit information. Moreover, we also introduce a modest hardware feature, called Address Translation Counters (ATC) and compare its effectiveness with other sources of hardware
Results 11 - 20
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22
