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Entropy-Based Low Power Data TLB Design

by Chinnakrishnan Ballapuram, Gabriel H. Loh, Kiran Puttaswamy, Hsien-hsin S. Lee - In Proc. of the Intnl. Conf. on Compilers, Architecture, and Synthesis for Embedded Systems , 2006
"... The Translation Look-aside Buffer (TLB), a content addressable memory, consumes significant power due to the associative search mechanism it uses in the virtual to physical address translation. Based on our analysis of the TLB accesses, we make two observations. First, the entropy or information con ..."
Abstract - Cited by 2 (1 self) - Add to MetaCart
The Translation Look-aside Buffer (TLB), a content addressable memory, consumes significant power due to the associative search mechanism it uses in the virtual to physical address translation. Based on our analysis of the TLB accesses, we make two observations. First, the entropy or information

Reducing dTLB Energy Through Dynamic Resizing

by Delaluz Kandemir Sivasubramaniam, V. Delaluz, A. Sivasubramaniam, M. J. Irwin, N. Vijaykrishnan
"... Translation Look-aside Buffer (TLB), which is small Content Addressable Memory (CAM) structure used to translate virtual addresses to physical addresses, can consume significant energy in some architectures. In addition, its power density is high, due to its small area. Consequently, reducing power ..."
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Translation Look-aside Buffer (TLB), which is small Content Addressable Memory (CAM) structure used to translate virtual addresses to physical addresses, can consume significant energy in some architectures. In addition, its power density is high, due to its small area. Consequently, reducing power

Improving TLB Energy for Java Applications on JVM

by Chinnakrishnan S. Ballapuram, Hsien-hsin S. Lee
"... AbstractJava platforms are widely deployed and used rang-ing from ultra-mobile embedded devices to servers for their portability and security. The TLB, a content addressable memory, can consume a signicant power in these systems due to the nature of its associative search mechanism. In this paper, w ..."
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AbstractJava platforms are widely deployed and used rang-ing from ultra-mobile embedded devices to servers for their portability and security. The TLB, a content addressable memory, can consume a signicant power in these systems due to the nature of its associative search mechanism. In this paper

A case study of a hardware-managed TLB in a multi-tasking environment

by Chih-chieh Lee, Richard A. Uhlig, Trevor N. Mudge , 1994
"... There have been very few performance studies of hardware-managed translation look-aside buffers (TLBs).The major reason is the lack of efficient and accurate analysis tools. Newer operating systems, applications, and the popularity of the client-server model of computation place a greater burden tha ..."
Abstract - Cited by 2 (0 self) - Add to MetaCart
to evaluate the performance of a range of TLBs under these newer workloads. The results show that in order to improve the TLB performance, we should carefully map pages into the TLB, append process identifiers to avoid flushing the TLB contents frequently, or reserve part of the TLB for a particular server

A Case Study of a Hardware-ManagedTLB in a Multi-Tasking Environment

by Chih-Chieh Lee, Richard A. Uhlig, Trevor N. Mudge , 1994
"... There have been very few performance studies of hardware-managed translation look-aside buffers (TLBs).The major reason is the lack of efficient and accurate analysis tools. Newer operating systems, applications, and the popularity of the client-server model of computation place a greater burden tha ..."
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to evaluate the performance of a range of TLBs under these newer workloads. The results show that in order to improve the TLB performance, we should carefully map pages into the TLB, append process identifiers to avoid flushing the TLB contents frequently, or reserve part of the TLB for a particular server

Compiler-Directed Code Restructuring for Reducing Data TLB energy

by M. Kandemir, I. Kadayif, G. Chen - In Proceedings International Conference on Hardware/Software Codesign and System Synthesis , 2004
"... Prior work on TLB power optimization considered circuit and architectural techniques. A recent software-based technique for data TLBs has considered the possibility of storing the frequently used virtual-to-physical address translations in a set of translation registers (TRs), and using them when ne ..."
Abstract - Cited by 4 (0 self) - Add to MetaCart
necessary instead of going to the data TLB. This paper presents a compiler-based strategy for increasing the effectiveness of TRs. The idea is to restructure the application code in such a fashion that once a TR is loaded, its contents are reused as much as possible. Our experimental evaluation with six

Contents lists available at SciVerse ScienceDirect Journal of Systems Architecture

by unknown authors
"... journal homepage: www.elsevier.com/locate/sysarc Reducing cache and TLB power by exploiting memory region and privilege ..."
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journal homepage: www.elsevier.com/locate/sysarc Reducing cache and TLB power by exploiting memory region and privilege

POSTPRINT VERSION, COPYRIGHT OWNED BY IEEE On the Performance of Tagged Translation Lookaside Buffers: A Simulation-Driven Analysis

by Girish Venkatasubramanian, Renato J. Figueiredo, Ramesh Illikkal
"... Abstract—Recent virtualization-driven CPU architectural extensions involve tagging the hardware-managed Translation Lookaside Buffer (TLB) entries to avoid TLB flushes during context switches, thereby sharing the TLB among multiple address spaces. While tagged TLBs are expected to improve the perfor ..."
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the performance of virtualized workloads, a systematic evaluation of this improvement, its dependence on TLB and workload related factors and the performance implications of the con-tention arising from TLB sharing are yet to be investigated. This paper undertakes these investigations using a simulation

Dynamic Heterogeneity and the Need for Multicore virtualization

by Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi
"... As the computing industry enters the multicore era, exponential growth in the number of transistors on a chip continues to present challenges and opportunities for computer architects and system designers. We examine one emerging issue in particular: that of dynamic heterogeneity, which can arise, e ..."
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, even among physically homogeneous cores, from changing reliability, power, or thermal conditions, or different cache and TLB contents. This heterogeneity results in a constantly varying pool of hardware resources, which greatly complicates software’s traditional task of assigning computation to cores

ABSTRACT Title of Document: USING HARDWARE MONITORS TO AUTOMATICALLY IMPROVE MEMORY PERFORMANCE

by unknown authors
"... In this thesis, we propose and evaluate several techniques to dynamically increase the memory access locality of scientific and Java server applications running on cachecoherent non-uniform memory access(cc-NUMA) servers. We first introduce a userlevel online page migration scheme where applications ..."
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potential sources of profiles gathered from hardware monitors in dynamic page migration and compare their effectiveness to using profiles from centralized hardware monitors. In particular, we evaluate using profiles from on-chip CPU monitors, valid TLB content and a hypothetical hardware feature. We also
Results 1 - 10 of 22