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Multiprocessors and Thread-Level Parallelism

by n.n.
"... ..."
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In search of speculative thread-level parallelism

by Jeffrey T. Oplinger, David L. Heine, Monica S. Lam - In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques , 1999
"... This paper focuses on the problem of how to find and effectively exploit speculative thread-level parallelism. Our studies show that speculating only on loops does not yield sufficient parallelism. We propose the use of speculative procedure execution as a means to increase the available parallelism ..."
Abstract - Cited by 61 (1 self) - Add to MetaCart
This paper focuses on the problem of how to find and effectively exploit speculative thread-level parallelism. Our studies show that speculating only on loops does not yield sufficient parallelism. We propose the use of speculative procedure execution as a means to increase the available

Scalable Learning with Thread-Level Parallelism

by Karsten Steinhaeuser, Nitesh V. Chawla
"... A significant increase in the ability to collect and store diverse information over the past decade has led to an outright data explosion, providing larger and richer datasets than ever before. This proliferation in dataset size is accompanied by the dilemma of successfully analyzing this data to di ..."
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also defies the subsampling paradigm, as even a subsample of data runs well into Gigabytes. To counter this challenge, we exploit advances in multi-threaded processor technology. We explore massive thread-level parallelism – provided by the Cray MTA-2 – as a platform for scalable data mining. We

Thread Level Parallelism of Desktop Applications

by Krisztián Flautner, Rich Uhlig , 2000
"... Multiprocessing is already prevalent in servers, where multiple clients present an obvious source of thread level parallelism. The case for multiprocessing is less clear for desktop applications, however processor architects are already designing processors that count on the availability of concurre ..."
Abstract - Cited by 8 (3 self) - Add to MetaCart
Multiprocessing is already prevalent in servers, where multiple clients present an obvious source of thread level parallelism. The case for multiprocessing is less clear for desktop applications, however processor architects are already designing processors that count on the availability

Thread-level parallelism and interactive performance of desktop applications

by Krisztián Flautner, Rich Uhlig, Steve Reinhardt, Trevor Mudge - Proceedings of Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-IX , 2000
"... Multiprocessing is already prevalent in servers where multiple clients present an obvious source of thread-level parallelism. However, the case for multiprocessing is less clear for desktop applications. Nevertheless, architects are designing processors that count on the availability of thread-level ..."
Abstract - Cited by 39 (6 self) - Add to MetaCart
Multiprocessing is already prevalent in servers where multiple clients present an obvious source of thread-level parallelism. However, the case for multiprocessing is less clear for desktop applications. Nevertheless, architects are designing processors that count on the availability of thread-level

Exploiting Thread-Level Parallelism to Build Decision Trees

by Karsten Steinhaeuser, Nitesh V. Chawla, Peter M. Kogge
"... Abstract. Classification is an important data mining task, and decision trees have emerged as a popular classifier due to their simplicity and relatively low computational complexity. However, as datasets get extremely large, the time required to build a decision tree still becomes intractable. Henc ..."
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Architecture (MTA) and extend the idea by employing thread-level parallelism to reduce the execution time of the tree building process. Decision tree building is well-suited for such low-level parallelism as it requires a large number of independent computations. In this paper, we present the analysis

Evolution of thread-level parallelism in desktop applications

by Geoffrey Blake, Ronald G. Dreslinski, Trevor Mudge, Krisztián Flautner - In Proceedings of the 37th Annual International Symposium on Computer Architecture , 2010
"... As the effective limits of frequency and instruction level par-allelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing cores on a single chip each generation. The implicit expecta-tion is that software developers will write their applicatio ..."
Abstract - Cited by 19 (3 self) - Add to MetaCart
-plications on Microsoft Windows 7 and Apple’s OS X Snow Leopard, measuring Thread Level Parallelism on a high per-formance workstation and a low power desktop. In addition, we explore graphics processing units (GPUs) and their im-pact on chip multi-processing. We compare our findings to a study done 10 years ago which

Abstract Thread level parallelism of desktop applications

by unknown authors
"... Multiprocessing is already prevalent in servers, where multiple clients present an obvious source of thread level parallelism. The case for multiprocessing is less clear for desktop applications, however processor architects are already designing processors that count on the availability of concurre ..."
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Multiprocessing is already prevalent in servers, where multiple clients present an obvious source of thread level parallelism. The case for multiprocessing is less clear for desktop applications, however processor architects are already designing processors that count on the availability

Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading

by Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen - ACM Transactions on Computer Systems , 1997
"... This article explores parallel processing on an alternative architecture, simultaneous multithreading (SMT), which allows multiple threads to compete for and share all of the processor's resources every cycle. The most compelling reason for running parallel applications on an SMT processor is i ..."
Abstract - Cited by 145 (17 self) - Add to MetaCart
is its ability to use thread-level parallelism and instruction-level parallelism interchangeably. By permitting This research was supported by Digital Equipment Corporation, the Washington Technology Center, NSF PYI Award MIP-9058439, NSF grants MIP-9632977, CCR-9200832, and CCR9632769, DARPA grant F

Exploiting Thread-Level Parallelism On simultaneous multithreaded processors

by Jack Lee-jay Lo , 1998
"... This dissertation investigates techniques for promoting constructive sharing and efficient utilization of processor resources on simultaneous multithreaded processors. Simultaneous multithreading is an architecture that permits multiple threads to issue multiple instructions to the functional unit ..."
Abstract - Cited by 6 (0 self) - Add to MetaCart
This dissertation investigates techniques for promoting constructive sharing and efficient utilization of processor resources on simultaneous multithreaded processors. Simultaneous multithreading is an architecture that permits multiple threads to issue multiple instructions to the functional
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