Systolic architectures, which permit multiple computations for each memory access, can speed execution of

algorithms. The architecture of the network is sys-tolic and therefore it is suitable for parallel processing. We only have to add and connect modules for scaling. This paper covers the process from the systolic design of BSS to the hardware implementation using Xilinx FPGAs. The simulation results of our

In this paper, we describe a systematic method for mapping the problem of symmetrizing Hessenberg matrices onto systolic architectures. The starting point of our method is a graphical abstraction of the system of linear recurrence equations that specifies the problem. Using a procedure called

In this paper, we describe a methodology for mapping normal linear recurrence equations onto a spectrum of systolic architectures. First, we provide a method to map a system of directed recurrence equations, a subclass of linear recurrence equations, onto a very general architecture referred

In this paper, we describe a methodology for mapping linear recurrence equations to a spectrum of systolic architectures. First, we provide a method to map a system of directed recurrence equations, a subclass of linear recurrence equations, onto a very general architecture referred to as basic

nanoseconds. We selected a representative example of a FIR filter with binary weights, and verified using simulation results that the neural network yields weights that enable the filter to perform very close to the theoretical peak performance that one can obtain from the given filter. We showed that the conventional LMS approach is unable to match the performance of the neural network since it cannot select the correct minimum from all the possible minima of the error function. We showed that the FIR filter with binary weights coupled with the proposed iterative neural network procedure for obtaining the optimal weights, forms an extremely simple filter to implement in hardware with good performance characteristics.

A new parallel algorithm for signal processing and a parallel systolic architecture of a robust constant false alarm rate (CFAR) processor with post-detection integration and adaptive censoring (RACPI) is presented in the paper. This detector is effective in conditions of flow from strong impulse

this paper we shall propose a novel analog systolic architecture which is able to combine the main features of digital and analog solutions, providing in this way an efficient alternative for the implementation of fuzzy models. Furthermore, by using some of the organization principles

An area-eficzent systolic architecture for real-time, programmable-coeBcient jinite impulse response (FIR) filters is presented. A technique called pipelined clustering i s introduced t o derive the architecture in which a number of jilter t a p computations are multi-plexed in an appropriately

Abstract—An efficient self-configurable systolic architecture is