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Table 2: Different Switch Block Architectures Compared.

in FPGA Switch Block Layout and Evaluation
by Herman Schmit, et al.
"... In PAGE 7: ... the average node force metric, the brute force optimization tech- nique rediscovered all the optimal layouts for switch blocks with W lt;10. Table2 shows the average node force (AvgNode), maximum node force (MaxNode), and maximum single force (MaxForce) metric for a variety of switch block architectures as a function of size. The value shown in the table is the optimal obtaining using that metric as the goal (i.... In PAGE 7: ... Finally, we have mentioned that in the non-subset box there is some degree of freedom on the placement of the North-South switch in each column, and the East-West switch in each row. The metrics shown in the first three sets of columns in Table2 do not include these extra switches. This design freedom does not significantly tip the scales in favor of the non-subset switch blocks, however.... In PAGE 7: ... This design freedom does not significantly tip the scales in favor of the non-subset switch blocks, however. In the last set of columns in Table2 , under the label Subset+ we shown the same experiments and metrics for the subset switch block if the NS and WE switches are placed in the one reasonable location for them. These results still are significantly better than the non-subset switch block metrics.... ..."

Table 2: Margin Results for Switch Block Experiments

in On the Sensitivity of FPGA Architectural Conclusions to Experimental Assumptions, Tools, and Techniques
by Andy Yan, Rebecca Cheng, Steven J.E. Wilton
"... In PAGE 7: ...2) and different orthogonal assumptions (including values of Fc) but found that the conclusions were not strongly affected by these results. The graphs are not shown here, but are summarized in Table2 which shows the margin for the experimental variations that we investigated. Again, each experimental variation was labeled as not sensitive , slightly sensitive , sensitive , very sensitive and extremely sensitive , depending on the area*delay margin.... ..."

TABLE I UNCONNECTABILITY RATE OF DIFFERENT SWITCH BLOCK STRUCTURES AND FAULT TYPES

in Routability and Fault Tolerance of FPGA Interconnect Architectures
by Jing Huang, Mehdi Baradaran Tahoori, Fabrizio Lombardi

Table 3.4 Switch block parameters Parameter Description

in ARRAYS
by Kara Ka, Wing Poon, Kara Ka Wing Poon 2002

Tables 3 and 4 show the switch settings for the PC (and XT) motherboard. The PC has two eight- position switch blocks (Switch Block 1 and Switch Block 2), whereas the XT has only a single Switch Block 1. The PC used the additional switch block to control the amount of memory the system would recognize, and the XT automatically counted up the memory amount.

in unknown title
by unknown authors

Table 2: Channel width required for routing all nets keeping all switch blocks feasible.

in A New Global Routing Algorithm for FPGAs
by Yao-wen Chang, Shashidhar Thakur, Kai Zhu, D. F. Wong
"... In PAGE 5: ... Fig- ure 8 illustrates the switch block architecture. Table2 gives the comparison results of both classical and our routers for these benchmarks. The benchmark circuits in Table 1 were routed on the architecture using both, the traditional and our new, algorithms.... In PAGE 5: ... At the end of global routing, a switch block S is called feasible if there exists an rrv ~v 2 C ~ dS such that ~v dominates the corresponding ~ dS. Table2 lists the channel widths required for routing all the nets such that all switch blocks are feasible. It shows that our algorithm outperforms the old algorithms on all circuits and the classical router (old router) needs an average of 38% more channel width to route all nets than our router (new router) using the switch block shown in Figure 8.... ..."

Table 1. Complete switch block mappings used for white (CU) and black (CV) squares

in Analytical Framework for Switch Block Design
by Guy G. Lemieux, David M. Lewis 2002
"... In PAGE 5: ... These black switch blocks are characterized by their own mapping functions, CV. Ad hoc de- signs for various CV switch blocks, which are chosen to be slightly different from their CU counterparts, are shown in Table1 . In choosing the specific CVCT functions for the disjoint and universal-TG blocks, care is taken to preserve their layout structures by merely re-ordering the horizontal tracks.... ..."
Cited by 2

Table 1. Complete switch block mappings used for white (a0 ) and black (a1 ) squares

in Analytical Framework for Switch Block Design
by Guy G. Lemieux, David M. Lewis 2002
"... In PAGE 5: ... These black switch blocks are characterized by their own mapping functions, a5 . Ad hoc de- signs for various a5 switch blocks, which are chosen to be slightly different from their a0 counterparts, are shown in Table1 . In choosing the specific a5 a1 functions for the disjoint and universal-TG blocks, care is taken to preserve their layout structures by merely re-ordering the horizontal tracks.... ..."
Cited by 2

Table 3.5 Connection differences within a switch block when a bypass wire exists

in ARRAYS
by Kara Ka, Wing Poon, Kara Ka Wing Poon 2002

Table 1: Overhead of thread operations (in microseconds) spawn time join time context switch block thread unblock thread

in Exploitation of Multithreading to Improve Program Performance
by W.E. Cohen, N. Yalamanchilli, R. Tewari, C. Patel, T. Kazi
"... In PAGE 7: ... The times for the following operations were measured: creating a new thread, rejoining the parent thread, switching between two sibling threads, blocking on mutex condition, and resumption on mutex condition. Table1 summarizes the average timing for the various operations. Table 1: Overhead of thread operations (in microseconds) spawn time join time context switch block thread unblock thread... ..."
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