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Table 1: Sample Strict Policy Element Value

in Traceable and Automatic Compliance of Privacy Policies in Federated Digital Identity Management

by Anna C. Squicciarini, Abhilasha Bhargav-spantzel, Alexei Czeskis, Elisa Bertino

"... In PAGE 6: ...Table 2: Sample Moderate Policy Element Value Purpose current, pseudo-analysis, contact Access all Recipient ours, same Retention stated-purpose, legal-requirement The understanding of the policy illustrated in Table1 is that data may be used only for the current activity and cannot be shared with others. Element Recipient is set to ours, meaning that the owner has full access to data and (as by retention element) data is kept only as long as the purpose requires or as mandated by law.... In PAGE 6: ...ame business practices. Statistical records may be kept only with non-identifying information. The understanding of the Access element is that owner can be contacted with suggestions concerning treatments or drugs. As in the example of Table1 , owner has full access to data. Data is kept only as long as purpose requires or as mandated by law.... ..."

Table 1: Sample Strict Policy Element Value

in Traceable and Automatic Compliance of Privacy Policies in Federated Digital Identity Management

by unknown authors

Table 1-1 Ranking of APIs and their operation based on priority levels.

in unknown title

by unknown authors

"... In PAGE 24: ... optional: the implementation of this API is not strictly required. The ranking is listed in Table1... ..."

Table 2: Effects of Insertions and Deletions on the Covering, Onto, and Strictness Properties

in 3.2 Hierarchy Properties............................... 10

by Torben Bach, Pedersený Christian, S. Jensenþ, Curtis E. Dyreson 1999

"... In PAGE 32: ...1 Covering Hierarchies Modifications may render covering hierarchies non-covering in several ways. The the left-most table in Table2 , named Covering and discussed next, indicates whether an insertion ( Insert ) or a deletion ( Delete ) on the different parts of the input to MakeCovering may render the modified hierarchy non-covering. Problems may arise if links are inserted into CABVBNC0 that are not covered by insertions into CABVBNC8 and CAC8BNC0, or if links are deleted in CABVBNC8 or CAC8BNC0, but the corresponding BV-to-C0 links are not deleted in CABVBNC0.... In PAGE 32: ... C4 AW A1CXCABVBNC0 CJ A5BVBNC0B4A1CSCABVBNC8 BD CAC8BNC0B5 CJ A5BVBNC0B4CABVBNC8 BD A1CSCAC8BNC0B5 D2A5BVBNC0B4A1CXCABVBNC8 BD A1CXCAC8BNC0B5 D2 A1CSCABVBNC0 A.2 Onto Hierarchies The effects on the onto property of insertions and deletions are outlined in the middle table in Table2 . Insertion of values into C8 , deletion of values in BV, and deletion of links in CABVBNC8 may cause the hierarchy to become non-onto.... In PAGE 33: ... The introduction of non-strictness requires major restructuring of both the hierarchy and the pre-aggregated data, so this is reasonable. An overview of the effect on strictness of insertions and deletions in the input to algorithm MakeStrict is given in the right-most table in Table2 . If links are inserted into, or deleted from, CABVBNC8 or CAC8BNBZ, the links to C6 for the affected BV, C8 , and BZ values must be recomputed.... ..."

Table 1: Update-Open Intervals The interval is measured in seconds. The Pct accesses column indicates what percentage of the write-read dependencies occurred during the given time interval. The numbers in the quot;known 1USR quot; column indicate what percentage of dependencies during each time period could easily be seen to require strict_read.

in Service Interface and Replica Management Algorithm for Mobile File System Clients

by Carl D. Tait, Dan Duchamp 1991

"... In PAGE 6: ...2.2 Experiment 2: Choosing Between Strict and Loose Read The fourth column of Table1 shows the percent- age of those accesses made by applications that \ob- viously require quot; 1USR. This estimate was made by us based on our limited knowledge of a handful of applica- tions appearing in the traces, and therefore constitutes an underestimate of the ease with which the need for strict read can be judged.... ..."

Cited by 47

Table 1: Update-Open Intervals The interval is measured in seconds. The Pct accesses column indicates what percentage of the write-read dependencies occurred during the given time interval. The numbers in the ``known 1USR apos; apos; column indicate what percentage of dependencies during each time period could easily be seen to require strict_read.

in Service Interface and Replica Management Algorithm for Mobile File System Clients

by Carl Tait, Dan Duchamp 1991

Cited by 47

Table 1 illustrates the hierarchy of the Itanium memory model deflnition. Most constraints strictly follow the rules from [2]. We also explicitly add a pred- icate requireLinearOrder to capture the general ordering requirement since [2] has only English to convey this important ordering property.

in Analyzing the Intel Itanium memory ordering rules using logic programming and SAT

by Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom, Konrad Slind 2003

"... In PAGE 8: ...requireMemoryDataDependence requireReadValue - requireIrre exiveTotal - MD:RAW - validWr - requireTransitive - MD:WAR - validLocalWr - requireAsymmetric - MD:WAW - validRemoteWr - validDefaultWr requireWriteOperationOrder requireDataFlowDependence - validRd - local/remote case - DF:RAR - remote/remote case - DF:RAW requireNoUCBypasss - DF:WAR requireProgramOrder requireSequentialUC - acquire case requireCoherence - RAR case - release case - local/local case - RAW case - fence case - remote/remote case - WAR case - WAW case requireAtomicWBRelease Table1 . The speciflcation hierarchy of the Itanium memory ordering rules.... ..."

Cited by 11

Table 1 illustrates the hierarchy of the Itanium memory model definition. Most constraints strictly follow the rules from [2]. We also explicitly add a pred- icate requireLinearOrder to capture the general ordering requirement since [2] has only English to convey this important ordering property.

in Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT

by Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom, Konrad Slind 2003

"... In PAGE 7: ...requireMemoryDataDependence requireReadValue - requireIrreflexiveTotal - MD:RAW - validWr - requireTransitive - MD:WAR - validLocalWr - requireAsymmetric - MD:WAW - validRemoteWr - validDefaultWr requireWriteOperationOrder requireDataFlowDependence - validRd - local/remote case - DF:RAR - remote/remote case - DF:RAW requireNoUCBypasss - DF:WAR requireProgramOrder requireSequentialUC - acquire case requireCoherence - RAR case - release case - local/local case - RAW case - fence case - remote/remote case - WAR case - WAW case requireAtomicWBRelease Table1 . The specification hierarchy of the Itanium memory ordering rules.... ..."

Cited by 11

Table 1 illustrates the hierarchy of the Itanium memory model deflnition. Most constraints strictly follow the rules from [2]. We also explicitly add a pred- icate requireLinearOrder to capture the general ordering requirement since [2] has only English to convey this important ordering property.

in Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT

by Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom, Konrad Slind 2003

"... In PAGE 7: ...requireMemoryDataDependence requireReadValue - requireIrre exiveTotal - MD:RAW - validWr - requireTransitive - MD:WAR - validLocalWr - requireAsymmetric - MD:WAW - validRemoteWr - validDefaultWr requireWriteOperationOrder requireDataFlowDependence - validRd - local/remote case - DF:RAR - remote/remote case - DF:RAW requireNoUCBypasss - DF:WAR requireProgramOrder requireSequentialUC - acquire case requireCoherence - RAR case - release case - local/local case - RAW case - fence case - remote/remote case - WAR case - WAW case requireAtomicWBRelease Table1 . The speciflcation hierarchy of the Itanium memory ordering rules.... ..."

Cited by 11

Table 1 illustrates the hierarchy of the Itanium memory model deflnition. Most constraints strictly follow the rules from [2]. We also explicitly add a pred- icate requireLinearOrder to capture the general ordering requirement since [2] has only English to convey this important ordering property.

in Analyzing the Intel Itanium memory ordering rules using logic programming and SAT

by Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom, Konrad Slind 2003

"... In PAGE 8: ...requireMemoryDataDependence requireReadValue - requireWeakTotal - MD:RAW - validWr - requireTransitive - MD:WAR - validLocalWr - requireAsymmetric - MD:WAW - validRemoteWr - validDefaultWr requireWriteOperationOrder requireDataFlowDependence - validRd - local/remote case - DF:RAR - remote/remote case - DF:RAW requireNoUCBypasss - DF:WAR requireProgramOrder requireSequentialUC - acquire case requireCoherence - RAR case - release case - local/local case - RAW case - fence case - remote/remote case - WAR case - WAW case requireAtomicWBRelease Table1 . The speciflcation hierarchy of the Itanium memory ordering rules.... ..."

Cited by 11

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Table 1: Sample Strict Policy Element Value

Table 1: Sample Strict Policy Element Value

Table 1-1 Ranking of APIs and their operation based on priority levels.

Table 2: Effects of Insertions and Deletions on the Covering, Onto, and Strictness Properties

Table 1 illustrates the hierarchy of the Itanium memory model deflnition. Most constraints strictly follow the rules from [2]. We also explicitly add a pred- icate requireLinearOrder to capture the general ordering requirement since [2] has only English to convey this important ordering property.

Table 1 illustrates the hierarchy of the Itanium memory model definition. Most constraints strictly follow the rules from [2]. We also explicitly add a pred- icate requireLinearOrder to capture the general ordering requirement since [2] has only English to convey this important ordering property.

Table 1 illustrates the hierarchy of the Itanium memory model deflnition. Most constraints strictly follow the rules from [2]. We also explicitly add a pred- icate requireLinearOrder to capture the general ordering requirement since [2] has only English to convey this important ordering property.

Table 1 illustrates the hierarchy of the Itanium memory model deflnition. Most constraints strictly follow the rules from [2]. We also explicitly add a pred- icate requireLinearOrder to capture the general ordering requirement since [2] has only English to convey this important ordering property.